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|
/*
* drivers/net/ethernet/beckhoff/ec_bhf.c
*
* Copyright (C) 2014 Darek Marcinkiewicz <reksio@newterm.pl>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/* This is a driver for EtherCAT master module present on CCAT FPGA.
* Those can be found on Bechhoff CX50xx industrial PCs.
*/
#if 0
#define DEBUG
#endif
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ip.h>
#include <linux/skbuff.h>
#include <linux/hrtimer.h>
#include <linux/interrupt.h>
#include <linux/stat.h>
#define TIMER_INTERVAL_NSEC 20000
#define INFO_BLOCK_SIZE 0x10
#define INFO_BLOCK_TYPE 0x0
#define INFO_BLOCK_REV 0x2
#define INFO_BLOCK_BLK_CNT 0x4
#define INFO_BLOCK_TX_CHAN 0x4
#define INFO_BLOCK_RX_CHAN 0x5
#define INFO_BLOCK_OFFSET 0x8
#define EC_MII_OFFSET 0x4
#define EC_FIFO_OFFSET 0x8
#define EC_MAC_OFFSET 0xc
#define MAC_FRAME_ERR_CNT 0x0
#define MAC_RX_ERR_CNT 0x1
#define MAC_CRC_ERR_CNT 0x2
#define MAC_LNK_LST_ERR_CNT 0x3
#define MAC_TX_FRAME_CNT 0x10
#define MAC_RX_FRAME_CNT 0x14
#define MAC_TX_FIFO_LVL 0x20
#define MAC_DROPPED_FRMS 0x28
#define MAC_CONNECTED_CCAT_FLAG 0x78
#define MII_MAC_ADDR 0x8
#define MII_MAC_FILT_FLAG 0xe
#define MII_LINK_STATUS 0xf
#define FIFO_TX_REG 0x0
#define FIFO_TX_RESET 0x8
#define FIFO_RX_REG 0x10
#define FIFO_RX_ADDR_VALID (1u << 31)
#define FIFO_RX_RESET 0x18
#define DMA_CHAN_OFFSET 0x1000
#define DMA_CHAN_SIZE 0x8
#define DMA_WINDOW_SIZE_MASK 0xfffffffc
static struct pci_device_id ids[] = {
{ PCI_DEVICE(0x15ec, 0x5000), },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, ids);
struct rx_header {
#define RXHDR_NEXT_ADDR_MASK 0xffffffu
#define RXHDR_NEXT_VALID (1u << 31)
__le32 next;
#define RXHDR_NEXT_RECV_FLAG 0x1
__le32 recv;
#define RXHDR_LEN_MASK 0xfffu
__le16 len;
__le16 port;
__le32 reserved;
u8 timestamp[8];
} __packed;
#define PKT_PAYLOAD_SIZE 0x7e8
struct rx_desc {
struct rx_header header;
u8 data[PKT_PAYLOAD_SIZE];
} __packed;
struct tx_header {
__le16 len;
#define TX_HDR_PORT_0 0x1
#define TX_HDR_PORT_1 0x2
u8 port;
u8 ts_enable;
#define TX_HDR_SENT 0x1
__le32 sent;
u8 timestamp[8];
} __packed;
struct tx_desc {
struct tx_header header;
u8 data[PKT_PAYLOAD_SIZE];
} __packed;
#define FIFO_SIZE 64
static long polling_frequency = TIMER_INTERVAL_NSEC;
struct bhf_dma {
u8 *buf;
size_t len;
dma_addr_t buf_phys;
u8 *alloc;
size_t alloc_len;
dma_addr_t alloc_phys;
};
struct ec_bhf_priv {
struct net_device *net_dev;
struct pci_dev *dev;
void * __iomem io;
void * __iomem dma_io;
struct hrtimer hrtimer;
int tx_dma_chan;
int rx_dma_chan;
void * __iomem ec_io;
void * __iomem fifo_io;
void * __iomem mii_io;
void * __iomem mac_io;
struct bhf_dma rx_buf;
struct rx_desc *rx_descs;
int rx_dnext;
int rx_dcount;
struct bhf_dma tx_buf;
struct tx_desc *tx_descs;
int tx_dcount;
int tx_dnext;
u64 stat_rx_bytes;
u64 stat_tx_bytes;
};
#define PRIV_TO_DEV(priv) (&(priv)->dev->dev)
#define ETHERCAT_MASTER_ID 0x14
static void ec_bhf_print_status(struct ec_bhf_priv *priv)
{
struct device *dev = PRIV_TO_DEV(priv);
dev_dbg(dev, "Frame error counter: %d\n",
ioread8(priv->mac_io + MAC_FRAME_ERR_CNT));
dev_dbg(dev, "RX error counter: %d\n",
ioread8(priv->mac_io + MAC_RX_ERR_CNT));
dev_dbg(dev, "CRC error counter: %d\n",
ioread8(priv->mac_io + MAC_CRC_ERR_CNT));
dev_dbg(dev, "TX frame counter: %d\n",
ioread32(priv->mac_io + MAC_TX_FRAME_CNT));
dev_dbg(dev, "RX frame counter: %d\n",
ioread32(priv->mac_io + MAC_RX_FRAME_CNT));
dev_dbg(dev, "TX fifo level: %d\n",
ioread8(priv->mac_io + MAC_TX_FIFO_LVL));
dev_dbg(dev, "Dropped frames: %d\n",
ioread8(priv->mac_io + MAC_DROPPED_FRMS));
dev_dbg(dev, "Connected with CCAT slot: %d\n",
ioread8(priv->mac_io + MAC_CONNECTED_CCAT_FLAG));
dev_dbg(dev, "Link status: %d\n",
ioread8(priv->mii_io + MII_LINK_STATUS));
}
static void ec_bhf_reset(struct ec_bhf_priv *priv)
{
iowrite8(0, priv->mac_io + MAC_FRAME_ERR_CNT);
iowrite8(0, priv->mac_io + MAC_RX_ERR_CNT);
iowrite8(0, priv->mac_io + MAC_CRC_ERR_CNT);
iowrite8(0, priv->mac_io + MAC_LNK_LST_ERR_CNT);
iowrite32(0, priv->mac_io + MAC_TX_FRAME_CNT);
iowrite32(0, priv->mac_io + MAC_RX_FRAME_CNT);
iowrite8(0, priv->mac_io + MAC_DROPPED_FRMS);
iowrite8(0, priv->fifo_io + FIFO_TX_RESET);
iowrite8(0, priv->fifo_io + FIFO_RX_RESET);
iowrite8(0, priv->mac_io + MAC_TX_FIFO_LVL);
}
static void ec_bhf_send_packet(struct ec_bhf_priv *priv, struct tx_desc *desc)
{
u32 len = le16_to_cpu(desc->header.len) + sizeof(desc->header);
u32 addr = (u8 *)desc - priv->tx_buf.buf;
iowrite32((ALIGN(len, 8) << 24) | addr, priv->fifo_io + FIFO_TX_REG);
dev_dbg(PRIV_TO_DEV(priv), "Done sending packet\n");
}
static int ec_bhf_desc_sent(struct tx_desc *desc)
{
return le32_to_cpu(desc->header.sent) & TX_HDR_SENT;
}
static void ec_bhf_process_tx(struct ec_bhf_priv *priv)
{
if (unlikely(netif_queue_stopped(priv->net_dev))) {
/* Make sure that we perceive changes to tx_dnext. */
smp_rmb();
if (ec_bhf_desc_sent(&priv->tx_descs[priv->tx_dnext]))
netif_wake_queue(priv->net_dev);
}
}
static int ec_bhf_pkt_received(struct rx_desc *desc)
{
return le32_to_cpu(desc->header.recv) & RXHDR_NEXT_RECV_FLAG;
}
static void ec_bhf_add_rx_desc(struct ec_bhf_priv *priv, struct rx_desc *desc)
{
iowrite32(FIFO_RX_ADDR_VALID | ((u8 *)(desc) - priv->rx_buf.buf),
priv->fifo_io + FIFO_RX_REG);
}
static void ec_bhf_process_rx(struct ec_bhf_priv *priv)
{
struct rx_desc *desc = &priv
|