path: root/drivers/net/ethernet/dec/tulip/de4x5.h

/*
    Copyright 1994 Digital Equipment Corporation.

    This software may be used and distributed according to  the terms of the
    GNU General Public License, incorporated herein by reference.

    The author may    be  reached as davies@wanton.lkg.dec.com  or   Digital
    Equipment Corporation, 550 King Street, Littleton MA 01460.

    =========================================================================
*/

/*
** DC21040 CSR<1..15> Register Address Map
*/
#define DE4X5_BMR    iobase+(0x000 << lp->bus)  /* Bus Mode Register */
#define DE4X5_TPD    iobase+(0x008 << lp->bus)  /* Transmit Poll Demand Reg */
#define DE4X5_RPD    iobase+(0x010 << lp->bus)  /* Receive Poll Demand Reg */
#define DE4X5_RRBA   iobase+(0x018 << lp->bus)  /* RX Ring Base Address Reg */
#define DE4X5_TRBA   iobase+(0x020 << lp->bus)  /* TX Ring Base Address Reg */
#define DE4X5_STS    iobase+(0x028 << lp->bus)  /* Status Register */
#define DE4X5_OMR    iobase+(0x030 << lp->bus)  /* Operation Mode Register */
#define DE4X5_IMR    iobase+(0x038 << lp->bus)  /* Interrupt Mask Register */
#define DE4X5_MFC    iobase+(0x040 << lp->bus)  /* Missed Frame Counter */
#define DE4X5_APROM  iobase+(0x048 << lp->bus)  /* Ethernet Address PROM */
#define DE4X5_BROM   iobase+(0x048 << lp->bus)  /* Boot ROM Register */
#define DE4X5_SROM   iobase+(0x048 << lp->bus)  /* Serial ROM Register */
#define DE4X5_MII    iobase+(0x048 << lp->bus)  /* MII Interface Register */
#define DE4X5_DDR    iobase+(0x050 << lp->bus)  /* Data Diagnostic Register */
#define DE4X5_FDR    iobase+(0x058 << lp->bus)  /* Full Duplex Register */
#define DE4X5_GPT    iobase+(0x058 << lp->bus)  /* General Purpose Timer Reg.*/
#define DE4X5_GEP    iobase+(0x060 << lp->bus)  /* General Purpose Register */
#define DE4X5_SISR   iobase+(0x060 << lp->bus)  /* SIA Status Register */
#define DE4X5_SICR   iobase+(0x068 << lp->bus)  /* SIA Connectivity Register */
#define DE4X5_STRR   iobase+(0x070 << lp->bus)  /* SIA TX/RX Register */
#define DE4X5_SIGR   iobase+(0x078 << lp->bus)  /* SIA General Register */

/*
** EISA Register Address Map
*/
#define EISA_ID      iobase+0x0c80   /* EISA ID Registers */
#define EISA_ID0     iobase+0x0c80   /* EISA ID Register 0 */
#define EISA_ID1     iobase+0x0c81   /* EISA ID Register 1 */
#define EISA_ID2     iobase+0x0c82   /* EISA ID Register 2 */
#define EISA_ID3     iobase+0x0c83   /* EISA ID Register 3 */
#define EISA_CR      iobase+0x0c84   /* EISA Control Register */
#define EISA_REG0    iobase+0x0c88   /* EISA Configuration Register 0 */
#define EISA_REG1    iobase+0x0c89   /* EISA Configuration Register 1 */
#define EISA_REG2    iobase+0x0c8a   /* EISA Configuration Register 2 */
#define EISA_REG3    iobase+0x0c8f   /* EISA Configuration Register 3 */
#define EISA_APROM   iobase+0x0c90   /* Ethernet Address PROM */

/*
** PCI/EISA Configuration Registers Address Map
*/
#define PCI_CFID     iobase+0x0008   /* PCI Configuration ID Register */
#define PCI_CFCS     iobase+0x000c   /* PCI Command/Status Register */
#define PCI_CFRV     iobase+0x0018   /* PCI Revision Register */
#define PCI_CFLT     iobase+0x001c   /* PCI Latency Timer Register */
#define PCI_CBIO     iobase+0x0028   /* PCI Base I/O Register */
#define PCI_CBMA     iobase+0x002c   /* PCI Base Memory Address Register */
#define PCI_CBER     iobase+0x0030   /* PCI Expansion ROM Base Address Reg. */
#define PCI_CFIT     iobase+0x003c   /* PCI Configuration Interrupt Register */
#define PCI_CFDA     iobase+0x0040   /* PCI Driver Area Register */
#define PCI_CFDD     iobase+0x0041   /* PCI Driver Dependent Area Register */
#define PCI_CFPM     iobase+0x0043   /* PCI Power Management Area Register */

/*
** EISA Configuration Register 0 bit definitions
*/
#define ER0_BSW       0x80           /* EISA Bus Slave Width, 1: 32 bits */
#define ER0_BMW       0x40           /* EISA Bus Master Width, 1: 32 bits */
#define ER0_EPT       0x20           /* EISA PREEMPT Time, 0: 23 BCLKs */
#define ER0_ISTS      0x10           /* Interrupt Status (X) */
#define ER0_LI        0x08           /* Latch Interrupts */
#define ER0_INTL      0x06           /* INTerrupt Level */
#define ER0_INTT      0x01           /* INTerrupt Type, 0: Level, 1: Edge */

/*
** EISA Configuration Register 1 bit definitions
*/
#define ER1_IAM       0xe0           /* ISA Address Mode */
#define ER1_IAE       0x10           /* ISA Addressing Enable */
#define ER1_UPIN      0x0f           /* User Pins */

/*
** EISA Configuration Register 2 bit definitions
*/
#define ER2_BRS       0xc0           /* Boot ROM Size */
#define ER2_BRA       0x3c           /* Boot ROM Address <16:13> */

/*
** EISA Configuration Register 3 bit definitions
*/
#define ER3_BWE       0x40           /* Burst Write Enable */
#define ER3_BRE       0x04           /* Burst Read Enable */
#define ER3_LSR       0x02           /* Local Software Reset */

/*
** PCI Configuration ID Register (PCI_CFID). The Device IDs are left
** shifted 8 bits to allow detection of DC21142 and DC21143 variants with
** the configuration revision register step number.
*/
#define CFID_DID    0xff00           /* Device ID */
#define CFID_VID    0x00ff           /* Vendor ID */
#define DC21040_DID 0x0200           /* Unique Device ID # */
#define DC21040_VID 0x1011           /* DC21040 Manufacturer */
#define DC21041_DID 0x1400           /* Unique Device ID # */
#define DC21041_VID 0x1011           /* DC21041 Manufacturer */
#define DC21140_DID 0x0900           /* Unique Device ID # */
#define DC21140_VID 0x1011           /* DC21140 Manufacturer */
#define DC2114x_DID 0x1900           /* Unique Device ID # */
#define DC2114x_VID 0x1011           /* DC2114[23] Manufacturer */

/*
** Chipset defines
*/
#define DC21040     DC21040_DID
#define DC21041     DC21041_DID
#define DC21140     DC21140_DID
#define DC2114x     DC2114x_DID
#define DC21142     (DC2114x_DID | 0x0010)
#define DC21143     (DC2114x_DID | 0x0030)
#define DC2114x_BRK 0x0020           /* CFRV break between DC21142 & DC21143 */

#define is_DC21040 ((vendor == DC21040_VID) && (device == DC21040_DID))
#define is_DC21041 ((vendor == DC21041_VID) && (device == DC21041_DID))
#define is_DC21140 ((vendor == DC21140_VID) && (device == DC21140_DID))
#define is_DC2114x ((vendor == DC2114x_VID) && (device == DC2114x_DID))
#define is_DC21142 ((vendor == DC2114x_VID) && (device == DC21142))
#define is_DC21143 ((vendor == DC2114x_VID) && (device == DC21143))

/*
** PCI Configuration Command/Status Register (PCI_CFCS)
*/
#define CFCS_DPE    0x80000000       /* Detected Parity Error (S) */
#define CFCS_SSE    0x40000000       /* Signal System Error   (S) */
#define CFCS_RMA    0x20000000       /* Receive Master Abort  (S) */
#define CFCS_RTA    0x10000000       /* Receive Target Abort  (S) */
#define CFCS_DST    0x06000000       /* DEVSEL Timing         (S) */
#define CFCS_DPR    0x01000000       /* Data Parity Report    (S) */
#define CFCS_FBB    0x00800000       /* Fast Back-To-Back     (S) */
#define CFCS_SEE    0x00000100       /* System Error Enable   (C) */
#define CFCS_PER    0x00000040       /* Parity Error Response (C) */
#define CFCS_MO     0x00000004       /* Master Operation      (C) */
#define CFCS_MSA    0x00000002       /* Memory Space Access   (C) */
#define CFCS_IOSA   0x00000001       /* I/O Space Access      (C) */

/*
** PCI Configuration Revision Register (PCI_CFRV)
*/
#define CFRV_BC     0xff000000       /* Base Class */
#define CFRV_SC     0x00ff0000       /* Subclass */
#define CFRV_RN     0x000000f0       /* Revision Number */
#define CFRV_SN     0x0000000f       /* Step Number */
#define BASE_CLASS  0x02000000       /* Indicates Network Controller */
#define SUB_CLASS   0x00000000       /* Indicates Ethernet Controller */
#define STEP_NUMBER 0x00000020       /* Increments for future chips */
#define REV_NUMBER  0x00000003       /* 0x00, 0x01, 0x02, 0x03: Rev in Step */
#define CFRV_MASK   0xffff0000       /* Register mask */

/*
** PCI Configuration Latency Timer Register (PCI_CFLT)
*/
#define CFLT_BC     0x0000ff00       /* Latency Timer bits */

/*
** PCI Configuration Base I/O Address Register (PCI_CBIO)
*/
#define CBIO_MASK   -128             /* Base I/O Address Mask */
#define CBIO_IOSI   0x00000001       /* I/O Space Indicator (RO, value is 1) */

/*
** PCI Configuration Card Information Structure Register (PCI_CCIS)
*/
#define CCIS_ROMI   0xf0000000       /* ROM Image */
#define CCIS_ASO    0x0ffffff8       /* Address Space Offset */
#define CCIS_ASI    0x00000007       /* Address Space Indicator */

/*
** PCI Configuration Subsystem ID Register (PCI_SSID)
*/
#define SSID_SSID   0xffff0000       /* Subsystem ID */
#define SSID_SVID   0x0000ffff       /* Subsystem Vendor ID */

/*
** PCI Configuration Expansion ROM Base Address Register (PCI_CBER)
*/
#define CBER_MASK   0xfffffc00       /* Expansion ROM Base Address Mask */
#define CBER_ROME   0x00000001       /* ROM Enable */

/*
** PCI Configuration Interrupt Register (PCI_CFIT)
*/
#define CFIT_MXLT   0xff000000       /* MAX_LAT Value (0.25us periods) */
#define CFIT_MNGT   0x00ff0000       /* MIN_GNT Value (0.25us periods) */
#define CFIT_IRQP   0x0000ff00       /* Interrupt Pin */
#define CFIT_IRQL   0x000000ff       /* Interrupt Line */

/*
** PCI Configuration Power Management Area Register (PCI_CFPM)
*/
#define SLEEP       0x80             /* Power Saving Sleep Mode */
#define SNOOZE      0x40             /* Power Saving Snooze Mode */
#define WAKEUP      0x00             /* Power Saving Wakeup */

#define PCI_CFDA_DSU 0x41            /* 8 bit Configuration Space Address */
#define PCI_CFDA_PSM 0x43            /* 8 bit Configuration Space Address */

/*
** DC21040 Bus Mode Register (DE4X5_BMR)
*/
#define BMR_RML    0x00200000       /* [Memory] Read Multiple */
#define BMR_DBO    0x00100000       /* Descriptor Byte Ordering (Endian) */
#define BMR_TAP    0x000e0000       /* Transmit Automatic Polling */
#define BMR_DAS    0x00010000       /* Diagnostic Address Space */
#define BMR_CAL    0x0000c000       /* Cache Alignment */
#define BMR_PBL    0x00003f00       /* Programmable Burst Length */
#define BMR_BLE    0x00000080       /* Big/Little Endian */
#define BMR_DSL    0x0000007c       /* Descriptor Skip Length */
#define BMR_BAR    0x00000002       /* Bus ARbitration */
#define BMR_SWR    0x00000001       /* Software Reset */

                                    /* Timings here are for 10BASE-T/AUI only*/
#define TAP_NOPOLL 0x00000000       /* No automatic polling */
#define TAP_200US  0x00020000       /* TX automatic polling every 200us */
#define TAP_800US  0x00040000       /* TX automatic polling every 800us */
#define TAP_1_6MS  0x00060000       /* TX automatic polling every 1.6ms */
#define TAP_12_8US 0x00080000       /* TX automatic polling every 12.8us */
#define TAP_25_6US 0x000a0000       /* TX automatic polling every 25.6us */
#define TAP_51_2US 0x000c0000       /* TX automatic polling every 51.2us */
#define TAP_102_4US 0x000e0000      /* TX automatic polling every 102.4us */

#define CAL_NOUSE  0x00000000       /* Not used */
#define CAL_8LONG  0x00004000       /* 8-longword alignment */
#define CAL_16LONG 0x00008000       /* 16-longword alignment */
#define CAL_32LONG 0x0000c000       /* 32-longword alignment */

#define PBL_0      0x00000000       /*  DMA burst length = amount in RX FIFO */
#define PBL_1      0x00000100       /*  1 longword  DMA burst length */
#define PBL_2      0x00000200       /*  2 longwords DMA burst length */
#define PBL_4      0x00000400       /*  4 longwords DMA burst length */
#define PBL_8      0x00000800       /*  8 longwords DMA burst length */
#define PBL_16     0x00001000       /* 16 longwords DMA burst length */
#define PBL_32     0x00002000       /* 32 longwords DMA burst length */

#define DSL_0      0x00000000       /*  0 longword  / descriptor */
#define DSL_1      0x00000004       /*  1 longword  / descriptor */
#define DSL_2      0x00000008       /*  2 longwords / descriptor */
#define DSL_4      0x00000010       /*  4 longwords / descriptor */
#define DSL_8      0x00000020       /*  8 longwords / descriptor */
#define DSL_16     0x00000040       /* 16 longwords / descriptor */
#define DSL_32     0x00000080       /* 32 longwords / descriptor */

/*
** DC21040 Transmit Poll Demand Register (DE4X5_TPD)
*/
#define TPD        0x00000001       /* Transmit Poll Demand */

/*
** DC21040 Receive Poll Demand Register (DE4X5_RPD)
*/
#define RPD        0x00000001       /* Receive Poll Demand */

/*