path: root/drivers/net/ethernet/cortina/gemini.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Register definitions for Gemini GMAC Ethernet device driver
 *
 * Copyright (C) 2006 Storlink, Corp.
 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
 * Copytight (C) 2017 Linus Walleij <linus.walleij@linaro.org>
 */
#ifndef _GEMINI_ETHERNET_H
#define _GEMINI_ETHERNET_H

#include <linux/bitops.h>

/* Base Registers */
#define TOE_NONTOE_QUE_HDR_BASE		0x2000
#define TOE_TOE_QUE_HDR_BASE		0x3000

/* Queue ID */
#define TOE_SW_FREE_QID			0x00
#define TOE_HW_FREE_QID			0x01
#define TOE_GMAC0_SW_TXQ0_QID		0x02
#define TOE_GMAC0_SW_TXQ1_QID		0x03
#define TOE_GMAC0_SW_TXQ2_QID		0x04
#define TOE_GMAC0_SW_TXQ3_QID		0x05
#define TOE_GMAC0_SW_TXQ4_QID		0x06
#define TOE_GMAC0_SW_TXQ5_QID		0x07
#define TOE_GMAC0_HW_TXQ0_QID		0x08
#define TOE_GMAC0_HW_TXQ1_QID		0x09
#define TOE_GMAC0_HW_TXQ2_QID		0x0A
#define TOE_GMAC0_HW_TXQ3_QID		0x0B
#define TOE_GMAC1_SW_TXQ0_QID		0x12
#define TOE_GMAC1_SW_TXQ1_QID		0x13
#define TOE_GMAC1_SW_TXQ2_QID		0x14
#define TOE_GMAC1_SW_TXQ3_QID		0x15
#define TOE_GMAC1_SW_TXQ4_QID		0x16
#define TOE_GMAC1_SW_TXQ5_QID		0x17
#define TOE_GMAC1_HW_TXQ0_QID		0x18
#define TOE_GMAC1_HW_TXQ1_QID		0x19
#define TOE_GMAC1_HW_TXQ2_QID		0x1A
#define TOE_GMAC1_HW_TXQ3_QID		0x1B
#define TOE_GMAC0_DEFAULT_QID		0x20
#define TOE_GMAC1_DEFAULT_QID		0x21
#define TOE_CLASSIFICATION_QID(x)	(0x22 + x)	/* 0x22 ~ 0x2F */
#define TOE_TOE_QID(x)			(0x40 + x)	/* 0x40 ~ 0x7F */

/* TOE DMA Queue Size should be 2^n, n = 6...12
 * TOE DMA Queues are the following queue types:
 *		SW Free Queue, HW Free Queue,
 *		GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
 * The base address and descriptor number are configured at
 * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
 */
#define GET_WPTR(addr)			readw((addr) + 2)
#define GET_RPTR(addr)			readw((addr))
#define SET_WPTR(addr, data)		writew((data), (addr) + 2)
#define SET_RPTR(addr, data)		writew((data), (addr))
#define __RWPTR_NEXT(x, mask)		(((unsigned int)(x) + 1) & (mask))
#define __RWPTR_PREV(x, mask)		(((unsigned int)(x) - 1) & (mask))
#define __RWPTR_DISTANCE(r, w, mask)	(((unsigned int)(w) - (r)) & (mask))
#define __RWPTR_MASK(order)		((1 << (order)) - 1)
#define RWPTR_NEXT(x, order)		__RWPTR_NEXT((x), __RWPTR_MASK((order)))
#define RWPTR_PREV(x, order)		__RWPTR_PREV((x), __RWPTR_MASK((order)))
#define RWPTR_DISTANCE(r, w, order)	__RWPTR_DISTANCE((r), (w), \
						__RWPTR_MASK((order)))

/* Global registers */
#define GLOBAL_TOE_VERSION_REG		0x0000
#define GLOBAL_SW_FREEQ_BASE_SIZE_REG	0x0004
#define GLOBAL_HW_FREEQ_BASE_SIZE_REG	0x0008
#define GLOBAL_DMA_SKB_SIZE_REG		0x0010
#define GLOBAL_SWFQ_RWPTR_REG		0x0014
#define GLOBAL_HWFQ_RWPTR_REG		0x0018
#define GLOBAL_INTERRUPT_STATUS_0_REG	0x0020
#define GLOBAL_INTERRUPT_ENABLE_0_REG	0x0024
#define GLOBAL_INTERRUPT_SELECT_0_REG	0x0028
#define GLOBAL_INTERRUPT_STATUS_1_REG	0x0030
#define GLOBAL_INTERRUPT_ENABLE_1_REG	0x0034
#define GLOBAL_INTERRUPT_SELECT_1_REG	0x0038
#define GLOBAL_INTERRUPT_STATUS_2_REG	0x0040
#define GLOBAL_INTERRUPT_ENABLE_2_REG	0x0044
#define GLOBAL_INTERRUPT_SELECT_2_REG	0x0048
#define GLOBAL_INTERRUPT_STATUS_3_REG	0x0050
#define GLOBAL_INTERRUPT_ENABLE_3_REG	0x0054
#define GLOBAL_INTERRUPT_SELECT_3_REG	0x0058
#define GLOBAL_INTERRUPT_STATUS_4_REG	0x0060
#define GLOBAL_INTERRUPT_ENABLE_4_REG	0x0064
#define GLOBAL_INTERRUPT_SELECT_4_REG	0x0068
#define GLOBAL_HASH_TABLE_BASE_REG	0x006C
#define GLOBAL_QUEUE_THRESHOLD_REG	0x0070

/* GMAC 0/1 DMA/TOE register */
#define GMAC_DMA_CTRL_REG		0x0000
#define GMAC_TX_WEIGHTING_CTRL_0_REG	0x0004
#define GMAC_TX_WEIGHTING_CTRL_1_REG	0x0008
#define GMAC_SW_TX_QUEUE0_PTR_REG	0x000C
#define GMAC_SW_TX_QUEUE1_PTR_REG	0x0010
#define GMAC_SW_TX_QUEUE2_PTR_REG	0x0014
#define GMAC_SW_TX_QUEUE3_PTR_REG	0x0018
#define GMAC_SW_TX_QUEUE4_PTR_REG	0x001C
#define GMAC_SW_TX_QUEUE5_PTR_REG	0x0020
#define GMAC_SW_TX_QUEUE_PTR_REG(i)	(GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i))
#define GMAC_HW_TX_QUEUE0_PTR_REG	0x0024
#define GMAC_HW_TX_QUEUE1_PTR_REG	0x0028
#define GMAC_HW_TX_QUEUE2_PTR_REG	0x002C
#define GMAC_HW_TX_QUEUE3_PTR_REG	0x0030
#define GMAC_HW_TX_QUEUE_PTR_REG(i)	(GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i))
#define GMAC_DMA_TX_FIRST_DESC_REG	0x0038
#define GMAC_DMA_TX_CURR_DESC_REG	0x003C
#define GMAC_DMA_TX_DESC_WORD0_REG	0x0040
#define GMAC_DMA_TX_DESC_WORD1_REG	0x0044
#define GMAC_DMA_TX_DESC_WORD2_REG	0x0048
#define GMAC_DMA_TX_DESC_WORD3_REG	0x004C
#define GMAC_SW_TX_QUEUE_BASE_REG	0x0050
#define GMAC_HW_TX_QUEUE_BASE_REG	0x0054
#define GMAC_DMA_RX_FIRST_DESC_REG	0x0058
#define GMAC_DMA_RX_CURR_DESC_REG	0x005C
#define GMAC_DMA_RX_DESC_WORD0_REG	0x0060
#define GMAC_DMA_RX_DESC_WORD1_REG	0x0064
#define GMAC_DMA_RX_DESC_WORD2_REG	0x0068
#define GMAC_DMA_RX_DESC_WORD3_REG	0x006C
#define GMAC_HASH_ENGINE_REG0		0x0070
#define GMAC_HASH_ENGINE_REG1		0x0074
/* matching rule 0 Control register 0 */
#define GMAC_MR0CR0			0x0078
#define GMAC_MR0CR1			0x007C
#define GMAC_MR0CR2			0x0080
#define GMAC_MR1CR0			0x0084
#define GMAC_MR1CR1			0x0088
#define GMAC_MR1CR2			0x008C
#define GMAC_MR2CR0			0x0090
#define GMAC_MR2CR1			0x0094
#define GMAC_MR2CR2			0x0098
#define GMAC_MR3CR0			0x009C
#define GMAC_MR3CR1			0x00A0
#define GMAC_MR3CR2			0x00A4
/* Support Protocol Register 0 */
#define GMAC_SPR0			0x00A8
#define GMAC_SPR1			0x00AC
#define GMAC_SPR2			0x00B0
#define GMAC_SPR3			0x00B4
#define GMAC_SPR4			0x00B8
#define GMAC_SPR5			0x00BC
#define GMAC_SPR6			0x00C0
#define GMAC_SPR7			0x00C4
/* GMAC Hash/Rx/Tx AHB Weighting register */
#define GMAC_AHB_WEIGHT_REG		0x00C8

/* TOE GMAC 0/1 register */
#define GMAC_STA_ADD0			0x0000
#define GMAC_STA_ADD1			0x0004
#define GMAC_STA_ADD2			0x0008
#define GMAC_RX_FLTR			0x000c
#define GMAC_MCAST_FIL0			0x0010
#define GMAC_MCAST_FIL1			0x0014
#define GMAC_CONFIG0			0x0018
#define GMAC_CONFIG1			0x001c
#define GMAC_CONFIG2			0x0020
#define GMAC_CONFIG3			0x0024
#define GMAC_RESERVED			0x0028
#define GMAC_STATUS			0x002c
#define GMAC_IN_DISCARDS		0x0030
#define GMAC_IN_ERRORS			0x0034
#define GMAC_IN_MCAST			0x0038
#define GMAC_IN_BCAST			0x003c
#define GMAC_IN_MAC1			0x0040	/* for STA 1 MAC Address */
#define GMAC_IN_MAC2			0x0044	/* for STA 2 MAC Address */

#define RX_STATS_NUM	6

/* DMA Queues description Ring Base Address/Size Register (offset 0x0004) */
union dma_q_base_size {
	unsigned int bits32;
	unsigned int base_size;
};

#define DMA_Q_BASE_MASK		(~0x0f)

/* DMA SKB Buffer register (offset 0x0008) */
union dma_skb_size {
	unsigned int bits32;
	struct bit_0008 {
		unsigned int sw_skb_size : 16;	/* SW Free poll SKB Size */
		unsigned int hw_skb_size : 16;	/* HW Free poll SKB Size */
	} bits;
};

/* DMA SW Free Queue Read/Write Pointer Register (offset 0x000c) */
union dma_rwptr {
	unsigned int bits32;
	struct bit_000c {
		unsigned int rptr	: 16;	/* Read Ptr, RO */
		unsigned int wptr	: 16;	/* Write Ptr, RW */
	} bits;
};

/* Interrupt Status Register 0	(offset 0x0020)
 * Interrupt Mask Register 0	(offset 0x0024)
 * Interrupt Select Register 0	(offset 0x0028)
 */
#define GMAC1_TXDERR_INT_BIT		BIT(31)
#define GMAC1_TXPERR_INT_BIT		BIT(30)
#define GMAC0_TXDERR_INT_BIT		BIT(29)
#define GMAC0_TXPERR_INT_BIT		BIT(28)
#define GMAC1_RXDERR_INT_BIT		BIT(27)
#define GMAC1_RXPERR_INT_BIT		BIT(26)
#define GMAC0_RXDERR_INT_BIT		BIT(25)
#define GMAC0_RXPERR_INT_BIT		BIT(24)
#define GMAC1_SWTQ15_FIN_INT_BIT	BIT(23)
#define GMAC1_SWTQ14_FIN_INT_BIT	BIT(22)
#define GMAC1_SWTQ13_FIN_INT_BIT	BIT(21)
#define GMAC1_SWTQ12_FIN_INT_BIT	BIT(20)
#define GMAC1_SWTQ11_FIN_INT_BIT	BIT(19)
#define GMAC1_SWTQ10_FIN_INT_BIT	BIT(18)
#define GMAC0_SWTQ05_FIN_INT_BIT	BIT(17)
#define GMAC0_SWTQ04_FIN_INT_BIT	BIT(16)
#define GMAC0_SWTQ03_FIN_INT_BIT	BIT(15)
#define GMAC0_SWTQ02_FIN_INT_BIT	BIT(14)
#define GMAC0_SWTQ01_FIN_INT_BIT	BIT(13)
#define GMAC0_SWTQ00_FIN_INT_BIT	BIT(12)
#define GMAC1_SWTQ15_EOF_INT_BIT	BIT(11)
#define GMAC1_SWTQ14_EOF_INT_BIT	BIT(10)
#define GMAC1_SWTQ13_EOF_INT_BIT	BIT(9)
#define GMAC1_SWTQ12_EOF_INT_BIT	BIT(8)
#define GMAC1_SWTQ11_EOF_INT_BIT	BIT(7)
#define GMAC1_SWTQ10_EOF_INT_BIT	BIT(6)
#define GMAC0_SWTQ05_EOF_INT_BIT	BIT(5)
#define GMAC0_SWTQ04_EOF_INT_BIT	BIT(4)
#define GMAC0_SWTQ03_EOF_INT_BIT	BIT(3)
#define GMAC0_SWTQ02_EOF_INT_BIT	BIT(2)
#define GMAC0_SWTQ01_EOF_INT_BIT	BIT(1)
#define GMAC0_SWTQ00_EOF_INT_BIT	BIT(0)

/* Interrupt Status Register 1	(offset 0x0030)
 * Interrupt Mask Register 1	(offset 0x0034)
 * Interrupt Select Register 1	(offset 0x0038)
 */
#define TOE_IQ3_FULL_INT_BIT		BIT(31)
#define TOE_IQ2_FULL_INT_BIT		BIT(30)
#define TOE_IQ1_FULL_INT_BIT		BIT(29)
#define TOE_IQ0_FULL_INT_BIT		BIT(28)
#define TOE_IQ3_INT_BIT			BIT(27)
#define TOE_IQ2_INT_BIT			BIT(26)
#define TOE_IQ1_INT_BIT			BIT(25)
#define TOE_IQ0_INT_BIT			BIT(24)
#define GMAC1_HWTQ13_EOF_INT_BIT	BIT(23)
#define GMAC1_HWTQ12_EOF_INT_BIT	BIT(22)
#define GMAC1_HWTQ11_EOF_INT_BIT	BIT(21)
#define GMAC1_HWTQ10_EOF_INT_BIT	BIT(20)
#define GMAC0_HWTQ03_EOF_INT_BIT	BIT(19)
#define GMAC0_HWTQ02_EOF_INT_BIT	BIT(18)
#define GMAC0_HWTQ01_EOF_INT_BIT	BIT(17)
#define GMAC0_HWTQ00_EOF_INT_BIT	BIT(16)
#define CLASS_RX_INT_BIT(x)		BIT((x + 2))
#define DEFAULT_Q1_INT_BIT		BIT(1)
#define DEFAULT_Q0_INT_BIT		BIT(0)

#define TOE_IQ_INT_BITS		(TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
				 TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
#define	TOE_IQ_FULL_BITS	(TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
				 TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
#define	TOE_IQ_ALL_BITS		(TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
#define TOE_CLASS_RX_INT_BITS	0xfffc

/* Interrupt Status Register 2	(offset 0x0040)
 * Interrupt Mask Register 2	(offset 0x0044)
 * Interrupt Select Register 2	(offset 0x0048)
 */
#define TOE_QL_FULL_INT_BIT(x)		BIT(x)

/* Interrupt Status Register 3	(offset 0x0050)
 * Interrupt Mask Register 3	(offset 0x0054)
 * Interrupt Select Register 3	(offset 0x0058)
 */
#define TOE_QH_FULL_INT_BIT(x)		BIT(x - 32)

/* Interrupt Status Register 4	(offset 0x0060)
 * Interrupt Mask Register 4	(offset 0x0064)
 * Interrupt Select Register 4	(offset 0x0068)
 */
#define GMAC1_RESERVED_INT_BIT		BIT(31)
#define GMAC1_MIB_INT_BIT		BIT(30)
#define GMAC1_RX_PAUSE_ON_INT_BIT	BIT(29)
#define GMAC1_TX_PAUSE_ON_INT_BIT	BIT(28)
#define GMAC1_RX_PAUSE_OFF_INT_BIT	BIT(27)
#define GMAC1_TX_PAUSE_OFF_INT_BIT	BIT(26)
#define GMAC1_RX_OVERRUN_INT_BIT	BIT(25)
#define GMAC1_STATUS_CHANGE_INT_BIT	BIT(24)
#define GMAC0_RESERVED_INT_BIT		BIT(23)
#define GMAC0_MIB_INT_BIT		BIT(22)
#define GMAC0_RX_PAUSE_ON_INT_BIT	BIT(21)
#define GMAC0_TX_PAUSE_ON_INT_BIT	BIT(20)
#define GMAC0_RX_PAUSE_OFF_INT_BIT	BIT(19)
#define GMAC0_TX_PAUSE_OFF_INT_BIT	BIT(18)
#define GMAC0_RX_OVERRUN_INT_BIT	BIT(17)
#define GMAC0_STATUS_CHANGE_INT_BIT	BIT(16)
#define CLASS_RX_FULL_INT_BIT(x)	BIT(x + 2)
#define HWFQ_EMPTY_INT_BIT		BIT(1)
#define SWFQ_EMPTY_INT_BIT		BIT(0)

#define GMAC0_INT_BITS	(GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
			 GMAC0_RX_PAUSE_ON_INT_BIT | \
			 GMAC0_TX_PAUSE_ON_INT_BIT | \
			 GMAC0_RX_PAUSE_OFF_INT_BIT | \
			 GMAC0_TX_PAUSE_OFF_INT_BIT | \
			 GMAC0_RX_OVERRUN_INT_BIT | \
			 GMAC0_STATUS_CHANGE_INT_BIT)
#define GMAC1_INT_BITS	(GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
			 GMAC1_RX_PAUSE_ON_INT_BIT | \
			 GMAC1_TX_PAUSE_ON_INT_BIT | \
			 GMAC1_RX_PAUSE_OFF_INT_BIT | \
			 GMAC1_TX_PAUSE_OFF_INT_BIT | \
			 GMAC1_RX_OVERRUN_INT_BIT | \
			 GMAC1_STATUS_CHANGE_INT_BIT)

#define CLASS_RX_FULL_INT_BITS		0xfffc

/* GLOBAL_QUEUE_THRESHOLD_REG	(offset 0x0070) */
union queue_threshold {
	unsigned int bits32;
	struct bit_0070_2 {
		/*  7:0 Software Free Queue Empty Threshold */
		unsigned int swfq_empty:8;
		/* 15:8 Hardware Free Queue Empty Threshold */
		unsigned int hwfq_empty:8;
		/* 23:16 */
		unsigned int intrq:8;
		/* 31:24 */
		unsigned int toe_class:8;
	} bits;
};

/* GMAC DMA Control Register
 * GMAC0 offset 0x8000
 * GMAC1 offset 0xC000
 */
union gmac_dma_ctrl {
	unsigned int bits32;
	struct bit_8000 {
		/* bit 1:0 Peripheral Bus Width */
		unsigned int td_bus:2;
		/* bit 3:2 TxDMA max burst size for every AHB request *