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/*
* Copyright (C) 2015 Cavium, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License
* as published by the Free Software Foundation.
*/
#ifndef NIC_H
#define NIC_H
#include <linux/netdevice.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include "thunder_bgx.h"
/* PCI device IDs */
#define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E
#define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011
#define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034
#define PCI_DEVICE_ID_THUNDER_BGX 0xA026
/* Subsystem device IDs */
#define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E
#define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E
#define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E
#define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E
#define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134
#define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234
#define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334
/* PCI BAR nos */
#define PCI_CFG_REG_BAR_NUM 0
#define PCI_MSIX_REG_BAR_NUM 4
/* NIC SRIOV VF count */
#define MAX_NUM_VFS_SUPPORTED 128
#define DEFAULT_NUM_VF_ENABLED 8
#define NIC_TNS_BYPASS_MODE 0
#define NIC_TNS_MODE 1
/* NIC priv flags */
#define NIC_SRIOV_ENABLED BIT(0)
/* Min/Max packet size */
#define NIC_HW_MIN_FRS 64
#define NIC_HW_MAX_FRS 9190 /* Excluding L2 header and FCS */
/* Max pkinds */
#define NIC_MAX_PKIND 16
/* Max when CPI_ALG is IP diffserv */
#define NIC_MAX_CPI_PER_LMAC 64
/* NIC VF Interrupts */
#define NICVF_INTR_CQ 0
#define NICVF_INTR_SQ 1
#define NICVF_INTR_RBDR 2
#define NICVF_INTR_PKT_DROP 3
#define NICVF_INTR_TCP_TIMER 4
#define NICVF_INTR_MBOX 5
#define NICVF_INTR_QS_ERR 6
#define NICVF_INTR_CQ_SHIFT 0
#define NICVF_INTR_SQ_SHIFT 8
#define NICVF_INTR_RBDR_SHIFT 16
#define NICVF_INTR_PKT_DROP_SHIFT 20
#define NICVF_INTR_TCP_TIMER_SHIFT 21
#define NICVF_INTR_MBOX_SHIFT 22
#define NICVF_INTR_QS_ERR_SHIFT 23
#define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
#define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
#define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
#define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT)
#define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT)
#define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT)
#define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT)
/* MSI-X interrupts */
#define NIC_PF_MSIX_VECTORS 10
#define NIC_VF_MSIX_VECTORS 20
#define NIC_PF_INTR_ID_ECC0_SBE 0
#define NIC_PF_INTR_ID_ECC0_DBE 1
#define NIC_PF_INTR_ID_ECC1_SBE 2
#define NIC_PF_INTR_ID_ECC1_DBE 3
#define NIC_PF_INTR_ID_ECC2_SBE 4
#define NIC_PF_INTR_ID_ECC2_DBE 5
#define NIC_PF_INTR_ID_ECC3_SBE 6
#define NIC_PF_INTR_ID_ECC3_DBE 7
#define NIC_PF_INTR_ID_MBOX0 8
#define NIC_PF_INTR_ID_MBOX1 9
/* Minimum FIFO level before all packets for the CQ are dropped
*
* This value ensures that once a packet has been "accepted"
* for reception it will not get dropped due to non-availability
* of CQ descriptor. An errata in HW mandates this value to be
* atleast 0x100.
*/
#define NICPF_CQM_MIN_DROP_LEVEL 0x100
/* Global timer for CQ timer thresh interrupts
* Calculated for SCLK of 700Mhz
* value written should be a 1/16th of what is expected
*
* 1 tick per 0.025usec
*/
#define NICPF_CLK_PER_INT_TICK 1
/* Time to wait before we decide that a SQ is stuck.
*
* Since both pkt rx and tx notifications are done with same CQ,
* when packets are being received at very high rate (eg: L2 forwarding)
* then freeing transmitted skbs will be delayed and watchdog
* will kick in, resetting interface. Hence keeping this value high.
*/
#define NICVF_TX_TIMEOUT (50 * HZ)
struct nicvf_cq_poll {
struct nicvf *nicvf;
u8 cq_idx; /* Completion queue index */
struct napi_struct napi;
};
#define NIC_MAX_RSS_HASH_BITS 8
#define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
#define RSS_HASH_KEY_SIZE 5 /* 320 bit key */
struct nicvf_rss_info {
bool enable;
#define RSS_L2_EXTENDED_HASH_ENA BIT(0)
#define RSS_IP_HASH_ENA BIT(1)
#define RSS_TCP_HASH_ENA BIT(2)
#define RSS_TCP_SYN_DIS BIT(3)
#define RSS_UDP_HASH_ENA BIT(4)
#define RSS_L4_EXTENDED_HASH_ENA BIT(5)
#define RSS_ROCE_ENA BIT(6)
#define RSS_L3_BI_DIRECTION_ENA BIT(7)
#define RSS_L4_BI_DIRECTION_ENA BIT(8)
u64 cfg;
u8 hash_bits;
u16 rss_size;
u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
u64 key[RSS_HASH_KEY_SIZE];
} ____cacheline_aligned_in_smp;
struct nicvf_pfc {
u8 autoneg;
u8 fc_rx;
u8 fc_tx;
};
enum rx_stats_reg_offset {
RX_OCTS = 0x0,
RX_UCAST = 0x1,
RX_BCAST = 0x2,
RX_MCAST = 0x3,
RX_RED = 0x4,
RX_RED_OCTS = 0x5,
RX_ORUN = 0x6,
RX_ORUN_OCTS = 0x7,
RX_FCS = 0x8,
RX_L2ERR = 0x9,
RX_DRP_BCAST = 0xa,
RX_DRP_MCAST = 0xb,
RX_DRP_L3BCAST = 0xc,
RX_DRP_L3MCAST = 0xd,
RX_STATS_ENUM_LAST,
};
enum tx_stats_reg_offset {
TX_OCTS = 0x0,
TX_UCAST = 0x1,
TX_BCAST = 0x2,
TX_MCAST = 0x3,
TX_DROP = 0x4,
TX_STATS_ENUM_LAST,
};
struct nicvf_hw_stats {
u64 rx_bytes;
u64 rx_frames;
u64 rx_ucast_frames;
u64 rx_bcast_frames;
u64 rx_mcast_frames;
u64 rx_drops;
u64 rx_drop_red;
u64 rx_drop_red_bytes;
u64 rx_drop_overrun;
u64 rx_drop_overrun_bytes;
u64 rx_drop_bcast;
u64 rx_drop_mcast;
u64 rx_drop_l3_bcast;
u64 rx_drop_l3_mcast;
u64 rx_fcs_errors;
u64 rx_l2_errors;
u64 tx_bytes;
u64 tx_frames;
u64 tx_ucast_frames;
u64 tx_bcast_frames;
u64 tx_mcast_frames;
u64 tx_drops;
};
struct nicvf_drv_stats {
/* CQE Rx errs */
u64 rx_bgx_truncated_pkts;
u64 rx_jabber_errs;
u64 rx_fcs_errs;
u64 rx_bgx_errs;
u64 rx_prel2_errs;
u64 rx_l2_hdr_malformed;
u64 rx_oversize;
u64 rx_undersize;
u64 rx_l2_len_mismatch;
u64 rx_l2_pclp;
u64 rx_ip_ver_errs;
u64 rx_ip_csum_errs;
u64 rx_ip_hdr_malformed;
u64 rx_ip_payload_malformed;
u64 rx_ip_ttl_errs;
u64 rx_l3_pclp;
u64 rx_l4_malformed;
u64 rx_l4_csum_errs;
u64 rx_udp_len_errs;
u64 rx_l4_port_errs;
u64 rx_tcp_flag_errs;
u64 rx_tcp_offset_errs;
u64 rx_l4_pclp;
u64 rx_truncated_pkts;
/* CQE Tx errs */
u64 tx_desc_fault;
u64 tx_hdr_cons_err;
u64 tx_subdesc_err;
u64 tx_max_size_exceeded;
u64 tx_imm_size_oflow;
u64 tx_data_seq_err;
u64 tx_mem_seq_err;
u64 tx_lock_viol;
u64 tx_data_fault;
u64 tx_tstmp_conflict;
u64 tx_tstmp_timeout;
u64 tx_mem_fault;
u64 tx_csum_overlap;
u64 tx_csum_overflow;
/* driver debug stats */
u64 tx_tso;
u64 tx_timeout;
u64 txq_stop;
u64 txq_wake;
u64 rcv_buffer_alloc_failures;
u64 page_alloc;
struct u64_stats_sync syncp;
};
struct cavium_ptp;
struct xcast_addr_list {
int count;
u64 mc[];
};
struct nicvf_work {
struct work_struct work;
u8 mode;
struct xcast_addr_list *mc;
};
struct nicvf {
struct nicvf *pnicvf;
struct net_device *netdev;
struct pci_dev *pdev;
void __iomem *reg_base;
struct bpf_prog *xdp_prog;
#define MAX_QUEUES_PER_QSET 8
struct queue_set *qs;
void *iommu_domain;
u8 vf_id;
u8 sqs_id;
bool sqs_mode;
bool hw_tso;
bool t88;
/* Receive buffer alloc */
u32 rb_page_offset;
u16 rb_pageref;
bool rb_alloc_fail;
bool rb_work_scheduled;
struct page *rb_page;
struct delayed_work rbdr_work;
struct tasklet_struct rbdr_task;
/* Secondary Qset */
u8 sqs_count;
#define MAX_SQS_PER_VF_SINGLE_NODE 5
#define MAX_SQS_PER_VF 11
struct nicvf *snicvf[MAX_SQS_PER_VF];
/* Queue count */
u8 rx_queues;
u8 tx_queues;
u8 xdp_tx_queues;
u8 max_queues;
u8 node;
u8 cpi_alg;
bool link_up;
u8 mac_type;
u8 duplex;
u32 speed;
bool tns_mode;
bool loopback_supported;
struct nicvf_rss_info rss_info;
struct nicvf_pfc pfc;
struct tasklet_struct qs_err_task;
struct work_struct reset_task;
struct nicvf_work rx_mode_work;
/* spinlock to protect workqueue arguments from concurrent access */
spinlock_t rx_mode_wq_lock;
/* workqueue for handling kernel ndo_set_rx_mode() calls */
struct workqueue_struct *nicvf_rx_mode_wq;
/* mutex to protect VF's mailbox contents from concurrent access */
struct mutex rx_mode_mtx;
struct delayed_work link_change_work;
/* PTP timestamp */
struct cavium_ptp *ptp_clock;
/* Inbound timestamping is on */
bool hw_rx_tstamp;
/* When the packet that requires timestamping is sent, hardware inserts
* two entries to the completion queue. First is the regular
* CQE_TYPE_SEND entry that signals that the packet was sent.
* The second is CQE_TYPE_SEND_PTP that contains the actual timestamp
* for that packet.
* `ptp_skb` is initialized in the handler for the CQE_TYPE_SEND
* entry and is used and zeroed in the handler for the CQE_TYPE_SEND_PTP
* entry.
* So `ptp_skb` is used to hold the pointer to the packet between
* the calls to CQE_TYPE_SEND and CQE_TYPE_SEND_PTP handlers.
*/
struct sk_buff *ptp_skb;
/* `tx_ptp_skbs` is set when the hardware is sending a packet that
* requires timestamping. Cavium hardware can not process more than one
* such packet at once so this is set each time the driver submits
* a packet that requires timestamping to the send queue and clears
* each time it receives the entry on the completion queue saying
* that such packet was sent.
* So `tx_ptp_skbs` prevents driver from submitting more than one
* packet that requires timestamping to the hardware for transmitting.
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