1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
|
/**********************************************************************
* Author: Cavium, Inc.
*
* Contact: support@cavium.com
* Please include "LiquidIO" in the subject.
*
* Copyright (c) 2003-2015 Cavium, Inc.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium, Inc. for more information
**********************************************************************/
/*! \file liquidio_common.h
* \brief Common: Structures and macros used in PCI-NIC package by core and
* host driver.
*/
#ifndef __LIQUIDIO_COMMON_H__
#define __LIQUIDIO_COMMON_H__
#include "octeon_config.h"
#define LIQUIDIO_VERSION "1.1.9"
#define LIQUIDIO_MAJOR_VERSION 1
#define LIQUIDIO_MINOR_VERSION 1
#define LIQUIDIO_MICRO_VERSION 9
#define CONTROL_IQ 0
/** Tag types used by Octeon cores in its work. */
enum octeon_tag_type {
ORDERED_TAG = 0,
ATOMIC_TAG = 1,
NULL_TAG = 2,
NULL_NULL_TAG = 3
};
/* pre-defined host->NIC tag values */
#define LIO_CONTROL (0x11111110)
#define LIO_DATA(i) (0x11111111 + (i))
/* Opcodes used by host driver/apps to perform operations on the core.
* These are used to identify the major subsystem that the operation
* is for.
*/
#define OPCODE_CORE 0 /* used for generic core operations */
#define OPCODE_NIC 1 /* used for NIC operations */
#define OPCODE_LAST OPCODE_NIC
/* Subcodes are used by host driver/apps to identify the sub-operation
* for the core. They only need to by unique for a given subsystem.
*/
#define OPCODE_SUBCODE(op, sub) (((op & 0x0f) << 8) | ((sub) & 0x7f))
/** OPCODE_CORE subcodes. For future use. */
/** OPCODE_NIC subcodes */
/* This subcode is sent by core PCI driver to indicate cores are ready. */
#define OPCODE_NIC_CORE_DRV_ACTIVE 0x01
#define OPCODE_NIC_NW_DATA 0x02 /* network packet data */
#define OPCODE_NIC_CMD 0x03
#define OPCODE_NIC_INFO 0x04
#define OPCODE_NIC_PORT_STATS 0x05
#define OPCODE_NIC_MDIO45 0x06
#define OPCODE_NIC_TIMESTAMP 0x07
#define OPCODE_NIC_INTRMOD_CFG 0x08
#define OPCODE_NIC_IF_CFG 0x09
#define CORE_DRV_TEST_SCATTER_OP 0xFFF5
#define OPCODE_SLOW_PATH(rh) \
(OPCODE_SUBCODE(rh->r.opcode, rh->r.subcode) != \
OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA))
/* Application codes advertised by the core driver initialization packet. */
#define CVM_DRV_APP_START 0x0
#define CVM_DRV_NO_APP 0
#define CVM_DRV_APP_COUNT 0x2
#define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0)
#define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1)
#define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2)
#define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
/* Macro to increment index.
* Index is incremented by count; if the sum exceeds
* max, index is wrapped-around to the start.
*/
#define INCR_INDEX(index, count, max) \
do { \
if (((index) + (count)) >= (max)) \
index = ((index) + (count)) - (max); \
else \
index += (count); \
} while (0)
#define INCR_INDEX_BY1(index, max) \
do { \
if ((++(index)) == (max)) \
index = 0; \
} while (0)
#define DECR_INDEX(index, count, max) \
do { \
if ((count) > (index)) \
index = ((max) - ((count - index))); \
else \
index -= count; \
} while (0)
#define OCT_BOARD_NAME 32
#define OCT_SERIAL_LEN 64
/* Structure used by core driver to send indication that the Octeon
* application is ready.
*/
struct octeon_core_setup {
u64 corefreq;
char boardname[OCT_BOARD_NAME];
char board_serial_number[OCT_SERIAL_LEN];
u64 board_rev_major;
u64 board_rev_minor;
};
/*--------------------------- SCATTER GATHER ENTRY -----------------------*/
/* The Scatter-Gather List Entry. The scatter or gather component used with
* a Octeon input instruction has this format.
*/
struct octeon_sg_entry {
/** The first 64 bit gives the size of data in each dptr.*/
union {
u16 size[4];
u64 size64;
} u;
/** The 4 dptr pointers for this entry. */
u64 ptr[4];
};
#define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry))
/* \brief Add size to gather list
* @param sg_entry scatter/gather entry
* @param size size to add
* @param pos position to add it.
*/
static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
u16 size,
u32 pos)
{
#ifdef __BIG_ENDIAN_BITFIELD
sg_entry->u.size[pos] = size;
#else
sg_entry->u.size[3 - pos] = size;
#endif
}
/*------------------------- End Scatter/Gather ---------------------------*/
#define OCTNET_FRM_PTP_HEADER_SIZE 8
#define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */
#define OCTNET_MIN_FRM_SIZE 64
#define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE)
#define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE)
/** NIC Commands are sent using this Octeon Input Queue */
#define OCTNET_CMD_Q 0
/* NIC Command types */
#define OCTNET_CMD_CHANGE_MTU 0x1
#define OCTNET_CMD_CHANGE_MACADDR 0x2
#define OCTNET_CMD_CHANGE_DEVFLAGS 0x3
#define OCTNET_CMD_RX_CTL 0x4
#define OCTNET_CMD_SET_MULTI_LIST 0x5
#define OCTNET_CMD_CLEAR_STATS 0x6
/* command for setting the speed, duplex & autoneg */
#define OCTNET_CMD_SET_SETTINGS 0x7
#define OCTNET_CMD_SET_FLOW_CTL 0x8
#define OCTNET_CMD_MDIO_READ_WRITE 0x9
#define OCTNET_CMD_GPIO_ACCESS 0xA
#define OCTNET_CMD_LRO_ENABLE 0xB
#define OCTNET_CMD_LRO_DISABLE 0xC
#define OCTNET_CMD_SET_RSS 0xD
#define OCTNET_CMD_WRITE_SA 0xE
#define OCTNET_CMD_DELETE_SA 0xF
#define OCTNET_CMD_UPDATE_SA 0x12
#define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
#define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
#define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
#define OCTNET_CMD_VERBOSE_ENABLE 0x14
#define OCTNET_CMD_VERBOSE_DISABLE 0x15
/* RX(packets coming from wire) Checksum verification flags */
/* TCP/UDP csum */
#define CNNIC_L4SUM_VERIFIED 0x1
#define CNNIC_IPSUM_VERIFIED 0x2
#define CNNIC_TUN_CSUM_VERIFIED 0x4
#define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
/*LROIPV4 and LROIPV6 Flags*/
#define OCTNIC_LROIPV4 0x1
#define OCTNIC_LROIPV6 0x2
/* Interface flags communicated between host driver and core app. */
enum octnet_ifflags {
OCTNET_IFFLAG_PROMISC = 0x01,
OCTNET_IFFLAG_ALLMULTI = 0x02,
OCTNET_IFFLAG_MULTICAST = 0x04,
OCTNET_IFFLAG_BROADCAST = 0x08,
OCTNET_IFFLAG_UNICAST = 0x10
};
/* wqe
* --------------- 0
* | wqe word0-3 |
* --------------- 32
* | PCI IH |
* --------------- 40
* | RPTR |
* --------------- 48
* | PCI IRH |
* --------------- 56
* | OCT_NET_CMD |
* --------------- 64
* | Addtl 8-BData |
* | |
* ---------------
*/
union octnet_cmd {
u64 u64;
struct {
#ifdef __BIG_ENDIAN_BITFIELD
u64 cmd:5;
u64 more:6; /* How many udd words follow the command */
u64 param1:29;
u64 param2:16;
u64 param3:8;
#else
u64 param3:8;
u64 param2:16;
u64 param1:29;
u64 more:6;
u64 cmd:5;
#endif
} s;
};
#define OCTNET_CMD_SIZE (sizeof(union octnet_cmd))
/** Instruction Header */
struct octeon_instr_ih {
#ifdef __BIG_ENDIAN_BITFIELD
/** Raw mode indicator 1 = RAW */
u64 raw:1;
/** Gather indicator 1=gather*/
u64 gather:1;
/** Data length OR no. of entries in gather list */
u64 dlengsz:14;
/** Front Data size */
u64 fsz:6;
/** Packet Order / Work Unit selection (1 of 8)*/
u64 qos:3;
/** Core group selection (1 of 16) */
u64 grp:4;
/** Short Raw Packet Indicator 1=short raw pkt */
u64 rs:1;
/** Tag type */
u64 tagtype:2;
/** Tag Value */
u64 tag:32;
#else
/** Tag Value */
u64 tag:32;
/** Tag type */
u64 tagtype:2;
/** Short Raw Packet Indicator 1=short raw pkt */
u64 rs:1;
/** Core group selection (1 of 16) */
u64 grp:4;
/** Packet Order / Work Unit selection (1 of 8)*/
u64 qos:3;
/** Front Data size */
u64 fsz:6;
/** Data length OR no. of entries in gather list */
u64 dlengsz:14;
/** Gather indicator 1=gather*/
u64 gather:1;
/** Raw mode indicator 1 = RAW */
u64 raw:1;
#endif
};
/** Input Request Header */
struct octeon_instr_irh {
#ifdef __BIG_ENDIAN_BITFIELD
u64 opcode:4;
u64 rflag:1;
u64 subcode:7;
u64 len:3;
u64 rid:13;
u64 reserved:4;
u64 ossp:32; /* opcode/subcode specific parameters */
#else
u64 ossp:32; /* opcode/subcode specific parameters */
u64 reserved:4;
u64 rid:13;
u64 len:3;
u64 subcode:7;
u64 rflag:1;
u64 opcode:4;
#endif
};
/** Return Data Parameters */
struct octeon_instr_rdp {
#ifdef __BIG_ENDIAN_BITFIELD
u64 reserved:49;
u64 pcie_port:3;
u64 rlen:12;
#else
u64 rlen:12;
u64 pcie_port:3;
u64 reserved:49;
#endif
};
/** Receive Header */
union octeon_rh {
#ifdef __BIG_ENDIAN_BITFIELD
u64 u64;
struct {
u64 opcode:4;
u64 subcode:8;
u64 len:3; /** additional 64-bit words */
u64 rid:13; /** request id in response to pkt sent by host */
u64 reserved:4;
u64 ossp:32; /** opcode/subcode specific parameters */
} r;
struct {
u64 opcode:4;
u64 subcode:8;
u64 len:3; /** additional 64-bit words */
u64 rid:13; /** request id in response to pkt sent by host */
u64 extra:24;
u64 link:8;
u64 csum_verified:3; /** che
|