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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Marvell 88E6xxx Ethernet switch single-chip definition
*
* Copyright (c) 2008 Marvell Semiconductor
*/
#ifndef _MV88E6XXX_CHIP_H
#define _MV88E6XXX_CHIP_H
#include <linux/if_vlan.h>
#include <linux/irq.h>
#include <linux/gpio/consumer.h>
#include <linux/kthread.h>
#include <linux/phy.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/timecounter.h>
#include <net/dsa.h>
#define MV88E6XXX_N_FID 4096
/* PVT limits for 4-bit port and 5-bit switch */
#define MV88E6XXX_MAX_PVT_SWITCHES 32
#define MV88E6XXX_MAX_PVT_PORTS 16
#define MV88E6XXX_MAX_GPIO 16
enum mv88e6xxx_egress_mode {
MV88E6XXX_EGRESS_MODE_UNMODIFIED,
MV88E6XXX_EGRESS_MODE_UNTAGGED,
MV88E6XXX_EGRESS_MODE_TAGGED,
MV88E6XXX_EGRESS_MODE_ETHERTYPE,
};
enum mv88e6xxx_frame_mode {
MV88E6XXX_FRAME_MODE_NORMAL,
MV88E6XXX_FRAME_MODE_DSA,
MV88E6XXX_FRAME_MODE_PROVIDER,
MV88E6XXX_FRAME_MODE_ETHERTYPE,
};
/* List of supported models */
enum mv88e6xxx_model {
MV88E6085,
MV88E6095,
MV88E6097,
MV88E6123,
MV88E6131,
MV88E6141,
MV88E6161,
MV88E6165,
MV88E6171,
MV88E6172,
MV88E6175,
MV88E6176,
MV88E6185,
MV88E6190,
MV88E6190X,
MV88E6191,
MV88E6220,
MV88E6240,
MV88E6250,
MV88E6290,
MV88E6320,
MV88E6321,
MV88E6341,
MV88E6350,
MV88E6351,
MV88E6352,
MV88E6390,
MV88E6390X,
};
enum mv88e6xxx_family {
MV88E6XXX_FAMILY_NONE,
MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
MV88E6XXX_FAMILY_6095, /* 6092 6095 */
MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
MV88E6XXX_FAMILY_6250, /* 6220 6250 */
MV88E6XXX_FAMILY_6320, /* 6320 6321 */
MV88E6XXX_FAMILY_6341, /* 6141 6341 */
MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
};
struct mv88e6xxx_ops;
struct mv88e6xxx_info {
enum mv88e6xxx_family family;
u16 prod_num;
const char *name;
unsigned int num_databases;
unsigned int num_ports;
unsigned int num_internal_phys;
unsigned int num_gpio;
unsigned int max_vid;
unsigned int port_base_addr;
unsigned int phy_base_addr;
unsigned int global1_addr;
unsigned int global2_addr;
unsigned int age_time_coeff;
unsigned int g1_irqs;
unsigned int g2_irqs;
bool pvt;
/* Mark certain ports as invalid. This is required for example for the
* MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
* ports 2-4 are not routet to pins.
*/
unsigned int invalid_port_mask;
/* Multi-chip Addressing Mode.
* Some chips respond to only 2 registers of its own SMI device address
* when it is non-zero, and use indirect access to internal registers.
*/
bool multi_chip;
/* Dual-chip Addressing Mode
* Some chips respond to only half of the 32 SMI addresses,
* allowing two to coexist on the same SMI interface.
*/
bool dual_chip;
enum dsa_tag_protocol tag_protocol;
/* Mask for FromPort and ToPort value of PortVec used in ATU Move
* operation. 0 means that the ATU Move operation is not supported.
*/
u8 atu_move_port_mask;
const struct mv88e6xxx_ops *ops;
/* Supports PTP */
bool ptp_support;
};
struct mv88e6xxx_atu_entry {
u8 state;
bool trunk;
u16 portvec;
u8 mac[ETH_ALEN];
};
struct mv88e6xxx_vtu_entry {
u16 vid;
u16 fid;
u8 sid;
bool valid;
u8 member[DSA_MAX_PORTS];
u8 state[DSA_MAX_PORTS];
};
struct mv88e6xxx_bus_ops;
struct mv88e6xxx_irq_ops;
struct mv88e6xxx_gpio_ops;
struct mv88e6xxx_avb_ops;
struct mv88e6xxx_ptp_ops;
struct mv88e6xxx_irq {
u16 masked;
struct irq_chip chip;
struct irq_domain *domain;
unsigned int nirqs;
};
/* state flags for mv88e6xxx_port_hwtstamp::state */
enum {
MV88E6XXX_HWTSTAMP_ENABLED,
MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
};
struct mv88e6xxx_port_hwtstamp {
/* Port index */
int port_id;
/* Timestamping state */
unsigned long state;
/* Resources for receive timestamping */
struct sk_buff_head rx_queue;
struct sk_buff_head rx_queue2;
/* Resources for transmit timestamping */
unsigned long tx_tstamp_start;
struct sk_buff *tx_skb;
u16 tx_seq_id;
/* Current timestamp configuration */
struct hwtstamp_config tstamp_config;
};
struct mv88e6xxx_port {
struct mv88e6xxx_chip *chip;
int port;
u64 serdes_stats[2];
u64 atu_member_violation;
u64 atu_miss_violation;
u64 atu_full_violation;
u64 vtu_member_violation;
u64 vtu_miss_violation;
u8 cmode;
int serdes_irq;
};
struct mv88e6xxx_chip {
const struct mv88e6xxx_info *info;
/* The dsa_switch this private structure is related to */
struct dsa_switch *ds;
/* The device this structure is associated to */
struct device *dev;
/* This mutex protects the access to the switch registers */
struct mutex reg_lock;
/* The MII bus and the address on the bus that is used to
* communication with the switch
*/
const struct mv88e6xxx_bus_ops *smi_ops;
struct mii_bus *bus;
int sw_addr;
/* Handles automatic disabling and re-enabling of the PHY
* polling unit.
*/
const struct mv88e6xxx_bus_ops *phy_ops;
struct mutex ppu_mutex;
int ppu_disabled;
struct work_struct ppu_work;
struct timer_list ppu_timer;
/* This mutex serialises access to the statistics unit.
* Hold this mutex over snapshot + dump sequences.
*/
struct mutex stats_mutex;
/* A switch may have a GPIO line tied to its reset pin. Parse
* this from the device tree, and use it before performing
* switch soft reset.
*/
struct gpio_desc *reset;
/* set to size of eeprom if supported by the switch */
u32 eeprom_len;
/* List of mdio busses */
struct list_head mdios;
/* There can be two interrupt controllers, which are chained
* off a GPIO as interrupt source
*/
struct mv88e6xxx_irq g1_irq;
struct mv88e6xxx_irq g2_irq;
int irq;
int device_irq;
int watchdog_irq;
int atu_prob_irq;
int vtu_prob_irq;
struct kthread_worker *kworker;
struct kthread_delayed_work irq_poll_work;
/* GPIO resources */
u8 gpio_data[2];
/* This cyclecounter abstracts the switch PTP time.
* reg_lock must be held for any operation that read()s.
*/
struct cyclecounter tstamp_cc;
struct timecounter tstamp_tc;
struct delayed_work overflow_work;
struct ptp_clock *ptp_clock;
struct ptp_clock_info ptp_clock_info;
struct delayed_work tai_event_work;
struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
u16 trig_config;
u16 evcap_config;
u16 enable_count;
/* Per-port timestamping resources. */
struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
/* Array of port structures. */
struct mv88e6xxx_port ports[DSA_MAX_PORTS];
};
struct mv88e6xxx_bus_ops {
int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
};
struct mv88e6xxx_mdio_bus {
struct mii_bus *bus;
struct mv88e6xxx_chip *chip;
struct list_head list;
bool external;
};
struct mv88e6xxx_ops {
/* Switch Setup Errata, called early in the switch setup to
* allow any errata actions to be performed
*/
int (*setup_errata)(struct mv88e6xxx_chip *chip);
int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
/* Ingress Rate Limit unit (IRL) operations */
int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
int (*get_eeprom)(struct mv88e6xxx_chip *chip,
struct ethtool_eeprom *eeprom, u8 *data);
int (*set_eeprom)(struct mv88e6xxx_chip *chip,
struct ethtool_eeprom *eeprom, u8 *data);
int (*set_switch_mac)(struct
|