/*
* CAN bus driver for Bosch C_CAN controller
*
* Copyright (C) 2010 ST Microelectronics
* Bhupesh Sharma <bhupesh.sharma@st.com>
*
* Borrowed heavily from the C_CAN driver originally written by:
* Copyright (C) 2007
* - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
* - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
*
* TX and RX NAPI implementation has been borrowed from at91 CAN driver
* written by:
* Copyright
* (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
* (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
*
* Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
* Bosch C_CAN user manual can be obtained from:
* http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
* users_manual_c_can.pdf
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/version.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/if_arp.h>
#include <linux/if_ether.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/can.h>
#include <linux/can/dev.h>
#include <linux/can/error.h>
#include "c_can.h"
/* control register */
#define CONTROL_TEST BIT(7)
#define CONTROL_CCE BIT(6)
#define CONTROL_DISABLE_AR BIT(5)
#define CONTROL_ENABLE_AR (0 << 5)
#define CONTROL_EIE BIT(3)
#define CONTROL_SIE BIT(2)
#define CONTROL_IE BIT(1)
#define CONTROL_INIT BIT(0)
/* test register */
#define TEST_RX BIT(7)
#define TEST_TX1 BIT(6)
#define TEST_TX2 BIT(5)
#define TEST_LBACK BIT(4)
#define TEST_SILENT BIT(3)
#define TEST_BASIC BIT(2)
/* status register */
#define STATUS_BOFF BIT(7)
#define STATUS_EWARN BIT(6)
#define STATUS_EPASS BIT(5)
#define STATUS_RXOK BIT(4)
#define STATUS_TXOK BIT(3)
/* error counter register */
#define ERR_CNT_TEC_MASK 0xff
#define ERR_CNT_TEC_SHIFT 0
#define ERR_CNT_REC_SHIFT 8
#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
#define ERR_CNT_RP_SHIFT 15
#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
/* bit-timing register */
#define BTR_BRP_MASK 0x3f
#define BTR_BRP_SHIFT 0
#define BTR_SJW_SHIFT 6
#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
#define BTR_TSEG1_SHIFT 8
#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
#define BTR_TSEG2_SHIFT 12
#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
/* brp extension register */
#define BRP_EXT_BRPE_MASK 0x0f
#define BRP_EXT_BRPE_SHIFT 0
/* IFx command request */
#define IF_COMR_BUSY BIT(15)
/* IFx command mask */
#define IF_COMM_WR BIT(7)
#define IF_COMM_MASK BIT(6)
#define IF_COMM_ARB BIT(5)
#define IF_COMM_CONTROL BIT(4)
#define IF_COMM_CLR_INT_PND BIT(3)
#define IF_COMM_TXRQST BIT(2)
#define IF_COMM_DATAA BIT(1)
#define IF_COMM_DATAB BIT(0)
#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
IF_COMM_CONTROL | IF_COMM_TXRQST | \
IF_COMM_DATAA | IF_COMM_DATAB)
/* IFx arbitration */
#define IF_ARB_MSGVAL BIT(15)
#define IF_ARB_MSGXTD BIT(14)
#define IF_ARB_TRANSMIT BIT(13)
/* IFx message control */
#define IF_MCONT_NEWDAT BIT(15)
#define IF_MCONT_MSGLST BIT(14)
#define IF_MCONT_CLR_MSGLST (0 << 14)
#define IF_MCONT_INTPND BIT(13)
#define IF_MCONT_UMASK BIT(12)
#define IF_MCONT_TXIE BIT(11)
#define IF_MCONT_RXIE BIT(10)
#define IF_MCONT_RMTEN BIT(9)
#define IF_MCONT_TXRQST BIT(8)
#define IF_MCONT_EOB BIT(7)
#define IF_MCONT_DLC_MASK 0xf
/*
* IFx register masks:
* allow easy operation on 16-bit registers when the
* argument is 32-bit instead
*/
#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF)
#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16)
/* message object split */
#define C_CAN_NO_OF_OBJECTS 32
#define C_CAN_MSG_OBJ_RX_NUM 16
#define C_CAN_MSG_OBJ_TX_NUM 16
#define C_CAN_MSG_OBJ_RX_FIRST 1
#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
C_CAN_MSG_OBJ_RX_NUM - 1)
#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
C_CAN_MSG_OBJ_TX_NUM - 1)
#define C_CAN_MSG_OBJ_RX_SPLIT 9
#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
#define RECEIVE_OBJECT_BITS 0x0000ffff
/* status interrupt */
#define STATUS_INTERRUPT 0x8000
/* global interrupt masks */
#define ENABLE_ALL_INTERRUPTS 1
#define DISABLE_ALL_INTERRUPTS 0
/* minimum timeout for checking BUSY status */
#define MIN_TIMEOUT_VALUE 6
/* napi related */
#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
/* c_can lec values */
enum c_can_lec_type {
LEC_NO_ERROR = 0,
LEC_STUFF_ERROR,
LEC_FORM_ERROR,
LEC_ACK_ERROR,
LEC_BIT1_ERROR,
LEC_BIT0_ERROR,
LEC_CRC_ERROR,
LEC_UNUSED,
};
/*
* c_can error types:
* Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
*/
enum c_can_bus_error_types {
C_CAN_NO_ERROR = 0,
C_CAN_BUS_OFF,
C_CAN_ERROR_WARNING,
C_CAN_ERROR_PASSIVE,
};
static struct can_bittiming_const c_can_bittiming_const = {
.name = KBUILD_MODNAME,
.tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
.tseg1_max = 16,
.tseg2_min = 1, /* Time segment 2 = phase_seg2 */
.tseg2_max = 8,
.sjw_max = 4,
.brp_min = 1,
.brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
.brp_inc = 1,
};
static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
{
return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
C_CAN_MSG_OBJ_TX_FIRST;
}
static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
{
return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) +
C_CAN_MSG_OBJ_TX_FIRST;
}
static u32 c_can_read_reg32(struct c_can_priv *priv, void *reg)
{
u32 val = priv->read_reg(priv, reg);
val |= ((u32) priv->read_reg(priv, reg + 2)) << 16;
return val;