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|
/* bnx2x_cmn.h: Broadcom Everest network driver.
*
* Copyright (c) 2007-2010 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*
* Maintained by: Eilon Greenstein <eilong@broadcom.com>
* Written by: Eliezer Tamir
* Based on code from Michael Chan's bnx2 driver
* UDP CSUM errata workaround by Arik Gendelman
* Slowpath and fastpath rework by Vladislav Zolotarov
* Statistics and Link management by Yitchak Gertner
*
*/
#ifndef BNX2X_CMN_H
#define BNX2X_CMN_H
#include <linux/types.h>
#include <linux/netdevice.h>
#include "bnx2x.h"
/*********************** Interfaces ****************************
* Functions that need to be implemented by each driver version
*/
/**
* Initialize link parameters structure variables.
*
* @param bp
* @param load_mode
*
* @return u8
*/
u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
/**
* Configure hw according to link parameters structure.
*
* @param bp
*/
void bnx2x_link_set(struct bnx2x *bp);
/**
* Query link status
*
* @param bp
*
* @return 0 - link is UP
*/
u8 bnx2x_link_test(struct bnx2x *bp);
/**
* Handles link status change
*
* @param bp
*/
void bnx2x__link_status_update(struct bnx2x *bp);
/**
* MSI-X slowpath interrupt handler
*
* @param irq
* @param dev_instance
*
* @return irqreturn_t
*/
irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
/**
* non MSI-X interrupt handler
*
* @param irq
* @param dev_instance
*
* @return irqreturn_t
*/
irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
#ifdef BCM_CNIC
/**
* Send command to cnic driver
*
* @param bp
* @param cmd
*/
int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
/**
* Provides cnic information for proper interrupt handling
*
* @param bp
*/
void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
#endif
/**
* Enable HW interrupts.
*
* @param bp
*/
void bnx2x_int_enable(struct bnx2x *bp);
/**
* Disable interrupts. This function ensures that there are no
* ISRs or SP DPCs (sp_task) are running after it returns.
*
* @param bp
* @param disable_hw if true, disable HW interrupts.
*/
void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
/**
* Loads device firmware
*
* @param bp
*
* @return int
*/
int bnx2x_init_firmware(struct bnx2x *bp);
/**
* Init HW blocks according to current initialization stage:
* COMMON, PORT or FUNCTION.
*
* @param bp
* @param load_code: COMMON, PORT or FUNCTION
*
* @return int
*/
int bnx2x_init_hw(struct bnx2x *bp, u32 load_code);
/**
* Init driver internals:
* - rings
* - status blocks
* - etc.
*
* @param bp
* @param load_code COMMON, PORT or FUNCTION
*/
void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
/**
* Allocate driver's memory.
*
* @param bp
*
* @return int
*/
int bnx2x_alloc_mem(struct bnx2x *bp);
/**
* Release driver's memory.
*
* @param bp
*/
void bnx2x_free_mem(struct bnx2x *bp);
/**
* Bring up a leading (the first) eth Client.
*
* @param bp
*
* @return int
*/
int bnx2x_setup_leading(struct bnx2x *bp);
/**
* Setup non-leading eth Client.
*
* @param bp
* @param fp
*
* @return int
*/
int bnx2x_setup_multi(struct bnx2x *bp, int index);
/**
* Set number of quueus according to mode and number of available
* msi-x vectors
*
* @param bp
*
*/
void bnx2x_set_num_queues_msix(struct bnx2x *bp);
/**
* Cleanup chip internals:
* - Cleanup MAC configuration.
* - Close clients.
* - etc.
*
* @param bp
* @param unload_mode
*/
void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
/**
* Acquire HW lock.
*
* @param bp
* @param resource Resource bit which was locked
*
* @return int
*/
int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
/**
* Release HW lock.
*
* @param bp driver handle
* @param resource Resource bit which was locked
*
* @return int
*/
int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
/**
* Configure eth MAC address in the HW according to the value in
* netdev->dev_addr for 57711
*
* @param bp driver handle
* @param set
*/
void bnx2x_set_eth_mac_addr_e1h(struct bnx2x *bp, int set);
/**
* Configure eth MAC address in the HW according to the value in
* netdev->dev_addr for 57710
*
* @param bp driver handle
* @param set
*/
void bnx2x_set_eth_mac_addr_e1(struct bnx2x *bp, int set);
#ifdef BCM_CNIC
/**
* Set iSCSI MAC(s) at the next enties in the CAM after the ETH
* MAC(s). The function will wait until the ramrod completion
* returns.
*
* @param bp driver handle
* @param set set or clear the CAM entry
*
* @return 0 if cussess, -ENODEV if ramrod doesn't return.
*/
int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set);
#endif
/**
* Initialize status block in FW and HW
*
* @param bp driver handle
* @param sb host_status_block
* @param dma_addr_t mapping
* @param int sb_id
*/
void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
dma_addr_t mapping, int sb_id);
/**
* Reconfigure FW/HW according to dev->flags rx mode
*
* @param dev net_device
*
*/
void bnx2x_set_rx_mode(struct net_device *dev);
/**
* Configure MAC filtering rules in a FW.
*
* @param bp driver handle
*/
void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
/* Parity errors related */
void bnx2x_inc_load_cnt(struct bnx2x *bp);
u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
bool bnx2x_chk_parity_attn(struct bnx2x *bp);
bool bnx2x_reset_is_done(struct bnx2x *bp);
void bnx2x_disable_close_the_gate(struct bnx2x *bp);
/**
* Perform statistics handling according to event
*
* @param bp driver handle
* @param even tbnx2x_stats_event
*/
void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
/**
* Configures FW with client paramteres (like HW VLAN removal)
* for each active client.
*
* @param bp
*/
void bnx2x_set_client_config(struct bnx2x *bp);
/**
* Handle sp events
*
* @param fp fastpath handle for the event
* @param rr_cqe eth_rx_cqe
*/
void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
{
struct host_status_block *fpsb = fp->status_blk;
barrier(); /* status block is written to by the chip */
fp->fp_c_idx = fpsb->c_status_block.status_block_index;
fp->fp_u_idx = fpsb->u_status_block.status_block_index;
}
static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
struct bnx2x_fastpath *fp,
u16 bd_prod, u16 rx_comp_prod,
u16 rx_sge_prod)
{
struct ustorm_eth_rx_producers rx_prods = {0};
int i;
/* Update producers */
rx_prods.bd_prod = bd_prod;
rx_prods.cqe_prod = rx_comp_prod;
rx_prods.sge_prod = rx_sge_prod;
/*
* Make sure that the BD and SGE data is updated before updating the
* producers since FW might read the BD/SGE right after the producer
* is updated.
* This is only applicable for weak-ordered memory model archs such
* as IA-64. The following barrier is also mandatory since FW will
* assumes BDs must have buffers.
*/
wmb();
for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
REG_WR(bp, BAR_USTRORM_INTMEM +
USTORM_RX_PRODS_OFFSET(BP_PORT(bp), fp->cl_id) + i*4,
((u32 *)&rx_prods)[i]);
mmiowb(); /* keep prod updates ordered */
DP(NETIF_MSG_RX_STATUS,
"queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
}
static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
u8 storm, u16 index, u8 op, u8 update)
{
u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
COMMAND_REG_INT_ACK);
struct igu_ack_register igu_ack;
igu_ack.status_block_index = index;
igu_ack.sb_id_and_flags =
((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
(storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
(update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
(op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
(*(u32
|