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|
/*
* EP93xx ethernet network device driver
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
* Dedicated to Marija Kulikova.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/mii.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/init.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <asm/arch/ep93xx-regs.h>
#include <asm/arch/platform.h>
#include <asm/io.h>
#define DRV_MODULE_NAME "ep93xx-eth"
#define DRV_MODULE_VERSION "0.1"
#define RX_QUEUE_ENTRIES 64
#define TX_QUEUE_ENTRIES 8
#define MAX_PKT_SIZE 2044
#define PKT_BUF_SIZE 2048
#define REG_RXCTL 0x0000
#define REG_RXCTL_DEFAULT 0x00073800
#define REG_TXCTL 0x0004
#define REG_TXCTL_ENABLE 0x00000001
#define REG_MIICMD 0x0010
#define REG_MIICMD_READ 0x00008000
#define REG_MIICMD_WRITE 0x00004000
#define REG_MIIDATA 0x0014
#define REG_MIISTS 0x0018
#define REG_MIISTS_BUSY 0x00000001
#define REG_SELFCTL 0x0020
#define REG_SELFCTL_RESET 0x00000001
#define REG_INTEN 0x0024
#define REG_INTEN_TX 0x00000008
#define REG_INTEN_RX 0x00000007
#define REG_INTSTSP 0x0028
#define REG_INTSTS_TX 0x00000008
#define REG_INTSTS_RX 0x00000004
#define REG_INTSTSC 0x002c
#define REG_AFP 0x004c
#define REG_INDAD0 0x0050
#define REG_INDAD1 0x0051
#define REG_INDAD2 0x0052
#define REG_INDAD3 0x0053
#define REG_INDAD4 0x0054
#define REG_INDAD5 0x0055
#define REG_GIINTMSK 0x0064
#define REG_GIINTMSK_ENABLE 0x00008000
#define REG_BMCTL 0x0080
#define REG_BMCTL_ENABLE_TX 0x00000100
#define REG_BMCTL_ENABLE_RX 0x00000001
#define REG_BMSTS 0x0084
#define REG_BMSTS_RX_ACTIVE 0x00000008
#define REG_RXDQBADD 0x0090
#define REG_RXDQBLEN 0x0094
#define REG_RXDCURADD 0x0098
#define REG_RXDENQ 0x009c
#define REG_RXSTSQBADD 0x00a0
#define REG_RXSTSQBLEN 0x00a4
#define REG_RXSTSQCURADD 0x00a8
#define REG_RXSTSENQ 0x00ac
#define REG_TXDQBADD 0x00b0
#define REG_TXDQBLEN 0x00b4
#define REG_TXDQCURADD 0x00b8
#define REG_TXDENQ 0x00bc
#define REG_TXSTSQBADD 0x00c0
#define REG_TXSTSQBLEN 0x00c4
#define REG_TXSTSQCURADD 0x00c8
#define REG_MAXFRMLEN 0x00e8
struct ep93xx_rdesc
{
u32 buf_addr;
u32 rdesc1;
};
#define RDESC1_NSOF 0x80000000
#define RDESC1_BUFFER_INDEX 0x7fff0000
#define RDESC1_BUFFER_LENGTH 0x0000ffff
struct ep93xx_rstat
{
u32 rstat0;
u32 rstat1;
};
#define RSTAT0_RFP 0x80000000
#define RSTAT0_RWE 0x40000000
#define RSTAT0_EOF 0x20000000
#define RSTAT0_EOB 0x10000000
#define RSTAT0_AM 0x00c00000
#define RSTAT0_RX_ERR 0x00200000
#define RSTAT0_OE 0x00100000
#define RSTAT0_FE 0x00080000
#define RSTAT0_RUNT 0x00040000
#define RSTAT0_EDATA 0x00020000
#define RSTAT0_CRCE 0x00010000
#define RSTAT0_CRCI 0x00008000
#define RSTAT0_HTI 0x00003f00
#define RSTAT1_RFP 0x80000000
#define RSTAT1_BUFFER_INDEX 0x7fff0000
#define RSTAT1_FRAME_LENGTH 0x0000ffff
struct ep93xx_tdesc
{
u32 buf_addr;
u32 tdesc1;
};
#define TDESC1_EOF 0x80000000
#define TDESC1_BUFFER_INDEX 0x7fff0000
#define TDESC1_BUFFER_ABORT 0x00008000
#define TDESC1_BUFFER_LENGTH 0x00000fff
struct ep93xx_tstat
{
u32 tstat0;
};
#define TSTAT0_TXFP 0x80000000
#define TSTAT0_TXWE 0x40000000
#define TSTAT0_FA 0x20000000
#define TSTAT0_LCRS 0x10000000
#define TSTAT0_OW 0x04000000
#define TSTAT0_TXU 0x02000000
#define TSTAT0_ECOLL 0x01000000
#define TSTAT0_NCOLL 0x001f0000
#define TSTAT0_BUFFER_INDEX 0x00007fff
struct ep93xx_descs
{
struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
};
struct ep93xx_priv
{
struct resource *res;
void *base_addr;
int irq;
struct ep93xx_descs *descs;
dma_addr_t descs_dma_addr;
void *rx_buf[RX_QUEUE_ENTRIES];
void *tx_buf[TX_QUEUE_ENTRIES];
spinlock_t rx_lock;
unsigned int rx_pointer;
unsigned int tx_clean_pointer;
unsigned int tx_pointer;
spinlock_t tx_pending_lock;
unsigned int tx_pending;
struct net_device *dev;
struct napi_struct napi;
struct net_device_stats stats;
struct mii_if_info mii;
u8 mdc_divisor;
};
#define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
#define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
#define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
#define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
#define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
#define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg);
static struct net_device_stats *ep93xx_get_stats(struct net_device *dev)
{
struct ep93xx_priv *ep = netdev_priv(dev);
return &(ep->stats);
}
static int ep93xx_rx(struct net_device *dev, int processed, int budget)
{
struct ep93xx_priv *ep = netdev_priv(dev);
while (processed < budget) {
int entry;
struct ep93xx_rstat *rstat;
u32 rstat0;
u32 rstat1;
int length;
struct sk_buff *skb;
entry = ep->rx_pointer;
rstat = ep->descs->rstat + entry;
rstat0 = rstat->rstat0;
rstat1 = rstat->rstat1;
if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
break;
rstat->rstat0 = 0;
rstat->rstat1 = 0;
if (!(rstat0 & RSTAT0_EOF))
printk(KERN_CRIT "ep93xx_rx: not end-of-frame "
" %.8x %.8x\n", rstat0, rstat1);
if (!(rstat0 & RSTAT0_EOB))
printk(KERN_CRIT "ep93xx_rx: not end-of-buffer "
" %.8x %.8x\n", rstat0, rstat1);
if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
printk(KERN_CRIT "ep93xx_rx: entry mismatch "
" %.8x %.8x\n", rstat0, rstat1);
if (!(rstat0 & RSTAT0_RWE)) {
ep->stats.rx_errors++;
if (rstat0 & RSTAT0_OE)
ep->stats.rx_fifo_errors++;
if (rstat0 & RSTAT0_FE)
ep->stats.rx_frame_errors++;
if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
ep->stats.rx_length_errors++;
if (rstat0 & RSTAT0_CRCE)
ep->stats.rx_crc_errors++;
goto err;
}
length = rstat1 & RSTAT1_FRAME_LENGTH;
if (length > MAX_PKT_SIZE)
|