/* * Driver for Cadence QSPI Controller * * Copyright Altera Corporation (C) 2012-2014. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along with * this program. If not, see <http://www.gnu.org/licenses/>. */#include<linux/clk.h>#include<linux/completion.h>#include<linux/delay.h>#include<linux/err.h>#include<linux/errno.h>#include<linux/interrupt.h>#include<linux/io.h>#include<linux/jiffies.h>#include<linux/kernel.h>#include<linux/module.h>#include<linux/mtd/mtd.h>#include<linux/mtd/partitions.h>#include<linux/mtd/spi-nor.h>#include<linux/of_device.h>#include<linux/of.h>#include<linux/platform_device.h>#include<linux/sched.h>#include<linux/spi/spi.h>#include<linux/timer.h>#define CQSPI_NAME "cadence-qspi"#define CQSPI_MAX_CHIPSELECT 16/* Quirks */#define CQSPI_NEEDS_WR_DELAY BIT(0)structcqspi_st;structcqspi_flash_pdata{structspi_nornor;structcqspi_st*cqspi;u32clk_rate;u32read_delay;u32tshsl_ns;u32tsd2d_ns;u32tchsh_ns;u32tslch_ns;u8inst_width;u8addr_width;u8data_width;u8cs;boolregistered;};structcqspi_st{structplatform_device*pdev;structclk*clk;unsignedintsclk;void__iomem*iobase;void__iomem*ahb_base;structcompletiontransfer_complete;structmutexbus_mutex;intcurrent_cs;intcurrent_page_size;intcurrent_erase_size;intcurrent_addr_width;unsignedlongmaster_ref_clk_hz;boolis_decoded_cs;u32fifo_depth;u32fifo_width;boolrclk_en;u32trigger_address;u32wr_delay;structcqspi_flash_pdataf_pdata[CQSPI_MAX_CHIPSELECT];};/* Operation timeout value */#define CQSPI_TIMEOUT_MS 500#define CQSPI_READ_TIMEOUT_MS 10/* Instruction type */#define CQSPI_INST_TYPE_SINGLE 0#define CQSPI_INST_TYPE_DUAL 1#define CQSPI_INST_TYPE_QUAD 2#define CQSPI_DUMMY_CLKS_PER_BYTE 8#define CQSPI_DUMMY_BYTES_MAX 4#define CQSPI_DUMMY_CLKS_MAX 31#define CQSPI_STIG_DATA_LEN_MAX 8/* Register map */#define CQSPI_REG_CONFIG 0x00#define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)#define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10#define CQSPI_REG_CONFIG_DMA_MASK BIT(15)#define CQSPI_REG_CONFIG_BAUD_LSB 19#define CQSPI_REG_CONFIG_IDLE_LSB 31#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF#define CQSPI_REG_CONFIG_BAUD_MASK 0xF#define CQSPI_REG_RD_INSTR 0x04#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0#define CQSPI_REG_RD_INSTR_T