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|
/*
* drivers/mtd/nand/rtc_from4.c
*
* Copyright (C) 2004 Red Hat, Inc.
*
* Derived from drivers/mtd/nand/spia.c
* Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
*
* $Id: rtc_from4.c,v 1.10 2005/11/07 11:14:31 gleixner Exp $
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Overview:
* This is a device driver for the AG-AND flash device found on the
* Renesas Technology Corp. Flash ROM 4-slot interface board (FROM_BOARD4),
* which utilizes the Renesas HN29V1G91T-30 part.
* This chip is a 1 GBibit (128MiB x 8 bits) AG-AND flash device.
*/
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/rslib.h>
#include <linux/bitrev.h>
#include <linux/module.h>
#include <linux/mtd/compatmac.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <asm/io.h>
/*
* MTD structure for Renesas board
*/
static struct mtd_info *rtc_from4_mtd = NULL;
#define RTC_FROM4_MAX_CHIPS 2
/* HS77x9 processor register defines */
#define SH77X9_BCR1 ((volatile unsigned short *)(0xFFFFFF60))
#define SH77X9_BCR2 ((volatile unsigned short *)(0xFFFFFF62))
#define SH77X9_WCR1 ((volatile unsigned short *)(0xFFFFFF64))
#define SH77X9_WCR2 ((volatile unsigned short *)(0xFFFFFF66))
#define SH77X9_MCR ((volatile unsigned short *)(0xFFFFFF68))
#define SH77X9_PCR ((volatile unsigned short *)(0xFFFFFF6C))
#define SH77X9_FRQCR ((volatile unsigned short *)(0xFFFFFF80))
/*
* Values specific to the Renesas Technology Corp. FROM_BOARD4 (used with HS77x9 processor)
*/
/* Address where flash is mapped */
#define RTC_FROM4_FIO_BASE 0x14000000
/* CLE and ALE are tied to address lines 5 & 4, respectively */
#define RTC_FROM4_CLE (1 << 5)
#define RTC_FROM4_ALE (1 << 4)
/* address lines A24-A22 used for chip selection */
#define RTC_FROM4_NAND_ADDR_SLOT3 (0x00800000)
#define RTC_FROM4_NAND_ADDR_SLOT4 (0x00C00000)
#define RTC_FROM4_NAND_ADDR_FPGA (0x01000000)
/* mask address lines A24-A22 used for chip selection */
#define RTC_FROM4_NAND_ADDR_MASK (RTC_FROM4_NAND_ADDR_SLOT3 | RTC_FROM4_NAND_ADDR_SLOT4 | RTC_FROM4_NAND_ADDR_FPGA)
/* FPGA status register for checking device ready (bit zero) */
#define RTC_FROM4_FPGA_SR (RTC_FROM4_NAND_ADDR_FPGA | 0x00000002)
#define RTC_FROM4_DEVICE_READY 0x0001
/* FPGA Reed-Solomon ECC Control register */
#define RTC_FROM4_RS_ECC_CTL (RTC_FROM4_NAND_ADDR_FPGA | 0x00000050)
#define RTC_FROM4_RS_ECC_CTL_CLR (1 << 7)
#define RTC_FROM4_RS_ECC_CTL_GEN (1 << 6)
#define RTC_FROM4_RS_ECC_CTL_FD_E (1 << 5)
/* FPGA Reed-Solomon ECC code base */
#define RTC_FROM4_RS_ECC (RTC_FROM4_NAND_ADDR_FPGA | 0x00000060)
#define RTC_FROM4_RS_ECCN (RTC_FROM4_NAND_ADDR_FPGA | 0x00000080)
/* FPGA Reed-Solomon ECC check register */
#define RTC_FROM4_RS_ECC_CHK (RTC_FROM4_NAND_ADDR_FPGA | 0x00000070)
#define RTC_FROM4_RS_ECC_CHK_ERROR (1 << 7)
#define ERR_STAT_ECC_AVAILABLE 0x20
/* Undefine for software ECC */
#define RTC_FROM4_HWECC 1
/* Define as 1 for no virtual erase blocks (in JFFS2) */
#define RTC_FROM4_NO_VIRTBLOCKS 0
/*
* Module stuff
*/
static void __iomem *rtc_from4_fio_base = (void *)P2SEGADDR(RTC_FROM4_FIO_BASE);
static const struct mtd_partition partition_info[] = {
{
.name = "Renesas flash partition 1",
.offset = 0,
.size = MTDPART_SIZ_FULL},
};
#define NUM_PARTITIONS 1
/*
* hardware specific flash bbt decriptors
* Note: this is to allow debugging by disabling
* NAND_BBT_CREATE and/or NAND_BBT_WRITE
*
*/
static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
static struct nand_bbt_descr rtc_from4_bbt_main_descr = {
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
.offs = 40,
.len = 4,
.veroffs = 44,
.maxblocks = 4,
.pattern = bbt_pattern
};
static struct nand_bbt_descr rtc_from4_bbt_mirror_descr = {
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
.offs = 40,
.len = 4,
.veroffs = 44,
.maxblocks = 4,
.pattern = mirror_pattern
};
#ifdef RTC_FROM4_HWECC
/* the Reed Solomon control structure */
static struct rs_control *rs_decoder;
/*
* hardware specific Out Of Band information
*/
static struct nand_ecclayout rtc_from4_nand_oobinfo = {
.eccbytes = 32,
.eccpos = {
0, 1, 2, 3, 4, 5, 6, 7,
8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27, 28, 29, 30, 31},
.oobfree = {{32, 32}}
};
#endif
/*
* rtc_from4_hwcontrol - hardware specific access to control-lines
* @mtd: MTD device structure
* @cmd: hardware control command
*
* Address lines (A5 and A4) are used to control Command and Address Latch
* Enable on this board, so set the read/write address appropriately.
*
* Chip Enable is also controlled by the Chip Select (CS5) and
* Address lines (A24-A22), so no action is required here.
*
*/
static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd,
unsigned int ctrl)
{
struct nand_chip *chip = (mtd->priv);
if (cmd == NAND_CMD_NONE)
return;
if (ctrl & NAND_CLE)
writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_CLE);
else
writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_ALE);
}
/*
* rtc_from4_nand_select_chip - hardware specific chip select
* @mtd: MTD device structure
* @chip: Chip to select (0 == slot 3, 1 == slot 4)
*
* The chip select is based on address lines A24-A22.
* This driver uses flash slots 3 and 4 (A23-A22).
*
*/
static void rtc_from4_nand_select_chip(struct mtd_info *mtd, int chip)
{
struct nand_chip *this = mtd->priv;
this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R & ~RTC_FROM4_NAND_ADDR_MASK);
this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_NAND_ADDR_MASK);
switch (chip) {
case 0: /* select slot 3 chip */
this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT3);
this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT3);
break;
case 1: /* select slot 4 chip */
this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT4);
this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT4);
break;
}
}
/*
* rtc_from4_nand_device_ready - hardware specific ready/busy check
* @mtd: MTD device structure
*
* This board provides the Ready/Busy state in the status register
* of the FPGA. Bit zero indicates the RDY(1)/BSY(0) signal.
*
*/
static int rtc_from4_nand_device_ready(struct mtd_info *mtd)
{
unsigned short status;
status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_FPGA_SR));
return (status & RTC_FROM4_DEVICE_READY);
}
/*
* deplete - code to perform device recovery in case there was a power loss
* @mtd: MTD device structure
* @chip: Chip to select (0 == slot 3, 1 == slot 4)
*
* If there was a sudden loss of power during an erase operation, a
* "device recovery" operation must be performed when power is restored
* to ensure correct operation. This routine performs the required steps
* for the requested chip.
*
* See page 86 of the data sheet for details.
*
*/
static void deplete(struct mtd_info *mtd, int chip)
{
struct nand_chip *this = mtd->priv;
/* wait until device is ready */
while (!this->dev_ready(mtd)) ;
this->select_chip(mtd, chip);
/* Send the commands for device recovery, phase 1 */
this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0000);
this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);
/* Send the commands for device recovery, phase 2 */
this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0004);
this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);
}
#ifdef RTC_FROM4_HWECC
/*
* rtc_from4_enable_hwecc - hardware specific hardware ECC enable function
* @mtd: MTD device structure
* @mode: I/O mode; read or write
*
* enable hardware ECC for data read or write
*
*/
static void rtc_from4_enable_hwecc(struct mtd_info *mtd, int mode)
{
volatile unsigned short *rs_ecc_ctl = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CTL);
unsigned short status;
switch (mode) {
case NAND_ECC_READ:
status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_FD_E;
*rs_ecc_ctl
|