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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Actions Semi Owl SoCs SD/MMC driver
*
* Copyright (c) 2014 Actions Semi Inc.
* Copyright (c) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*
* TODO: SDIO support
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-direction.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/reset.h>
#include <linux/spinlock.h>
/*
* SDC registers
*/
#define OWL_REG_SD_EN 0x0000
#define OWL_REG_SD_CTL 0x0004
#define OWL_REG_SD_STATE 0x0008
#define OWL_REG_SD_CMD 0x000c
#define OWL_REG_SD_ARG 0x0010
#define OWL_REG_SD_RSPBUF0 0x0014
#define OWL_REG_SD_RSPBUF1 0x0018
#define OWL_REG_SD_RSPBUF2 0x001c
#define OWL_REG_SD_RSPBUF3 0x0020
#define OWL_REG_SD_RSPBUF4 0x0024
#define OWL_REG_SD_DAT 0x0028
#define OWL_REG_SD_BLK_SIZE 0x002c
#define OWL_REG_SD_BLK_NUM 0x0030
#define OWL_REG_SD_BUF_SIZE 0x0034
/* SD_EN Bits */
#define OWL_SD_EN_RANE BIT(31)
#define OWL_SD_EN_RAN_SEED(x) (((x) & 0x3f) << 24)
#define OWL_SD_EN_S18EN BIT(12)
#define OWL_SD_EN_RESE BIT(10)
#define OWL_SD_EN_DAT1_S BIT(9)
#define OWL_SD_EN_CLK_S BIT(8)
#define OWL_SD_ENABLE BIT(7)
#define OWL_SD_EN_BSEL BIT(6)
#define OWL_SD_EN_SDIOEN BIT(3)
#define OWL_SD_EN_DDREN BIT(2)
#define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0)
/* SD_CTL Bits */
#define OWL_SD_CTL_TOUTEN BIT(31)
#define OWL_SD_CTL_TOUTCNT(x) (((x) & 0x7f) << 24)
#define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16)
#define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20)
#define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16)
#define OWL_SD_CTL_CMDLEN BIT(13)
#define OWL_SD_CTL_SCC BIT(12)
#define OWL_SD_CTL_TCN(x) (((x) & 0xf) << 8)
#define OWL_SD_CTL_TS BIT(7)
#define OWL_SD_CTL_LBE BIT(6)
#define OWL_SD_CTL_C7EN BIT(5)
#define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0)
#define OWL_SD_DELAY_LOW_CLK 0x0f
#define OWL_SD_DELAY_MID_CLK 0x0a
#define OWL_SD_DELAY_HIGH_CLK 0x09
#define OWL_SD_RDELAY_DDR50 0x0a
#define OWL_SD_WDELAY_DDR50 0x08
/* SD_STATE Bits */
#define OWL_SD_STATE_DAT1BS BIT(18)
#define OWL_SD_STATE_SDIOB_P BIT(17)
#define OWL_SD_STATE_SDIOB_EN BIT(16)
#define OWL_SD_STATE_TOUTE BIT(15)
#define OWL_SD_STATE_BAEP BIT(14)
#define OWL_SD_STATE_MEMRDY BIT(12)
#define OWL_SD_STATE_CMDS BIT(11)
#define OWL_SD_STATE_DAT1AS BIT(10)
#define OWL_SD_STATE_SDIOA_P BIT(9)
#define OWL_SD_STATE_SDIOA_EN BIT(8)
#define OWL_SD_STATE_DAT0S BIT(7)
#define OWL_SD_STATE_TEIE BIT(6)
#define OWL_SD_STATE_TEI BIT(5)
#define OWL_SD_STATE_CLNR BIT(4)
#define OWL_SD_STATE_CLC BIT(3)
#define OWL_SD_STATE_WC16ER BIT(2)
#define OWL_SD_STATE_RC16ER BIT(1)
#define OWL_SD_STATE_CRC7ER BIT(0)
struct owl_mmc_host {
struct device *dev;
struct reset_control *reset;
void __iomem *base;
struct clk *clk;
struct completion sdc_complete;
spinlock_t lock;
int irq;
u32 clock;
bool ddr_50;
enum dma_data_direction dma_dir;
struct dma_chan *dma;
struct dma_async_tx_descriptor *desc;
struct dma_slave_config dma_cfg;
struct completion dma_complete;
struct mmc_host *mmc;
struct mmc_request *mrq;
struct mmc_command *cmd;
struct mmc_data *data;
};
static void owl_mmc_update_reg(void __iomem *reg, unsigned int val, bool state)
{
unsigned int regval;
regval = readl(reg);
if (state)
regval |= val;
else
regval &= ~val;
writel(regval, reg);
}
static irqreturn_t owl_irq_handler(int irq, void *devid)
{
struct owl_mmc_host *owl_host = devid;
unsigned long flags;
u32 state;
spin_lock_irqsave(&owl_host->lock, flags);
state = readl(owl_host->base + OWL_REG_SD_STATE);
if (state & OWL_SD_STATE_TEI) {
state = readl(owl_host->base + OWL_REG_SD_STATE);
state |= OWL_SD_STATE_TEI;
writel(state, owl_host->base + OWL_REG_SD_STATE);
complete(&owl_host->sdc_complete);
}
spin_unlock_irqrestore(&owl_host->lock, flags);
return IRQ_HANDLED;
}
static void owl_mmc_finish_request(struct owl_mmc_host *owl_host)
{
struct mmc_request *mrq = owl_host->mrq;
struct mmc_data *data = mrq->data;
/* Should never be NULL */
WARN_ON(!mrq);
owl_host->mrq = NULL;
if (data)
dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len,
owl_host->dma_dir);
/* Finally finish request */
mmc_request_done(owl_host->mmc, mrq);
}
static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host,
struct mmc_command *cmd,
struct mmc_data *data)
{
u32 mode, state, resp[2];
u32 cmd_rsp_mask = 0;
init_completion(&owl_host->sdc_complete);
switch (mmc_resp_type(cmd)) {
case MMC_RSP_NONE:
mode = OWL_SD_CTL_TM(0);
break;
case MMC_RSP_R1:
if (data) {
if (data->flags & MMC_DATA_READ)
mode = OWL_SD_CTL_TM(4);
else
mode = OWL_SD_CTL_TM(5);
} else {
mode = OWL_SD_CTL_TM(1);
}
cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
break;
case MMC_RSP_R1B:
mode = OWL_SD_CTL_TM(3);
cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
break;
case MMC_RSP_R2:
mode = OWL_SD_CTL_TM(2);
cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
break;
case MMC_RSP_R3:
mode = OWL_SD_CTL_TM(1);
cmd_rsp_mask = OWL_SD_STATE_CLNR;
break;
default:
dev_warn(owl_host->dev, "Unknown MMC command\n");
cmd->error = -EINVAL;
return;
}
/* Keep current WDELAY and RDELAY */
mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
/* Start to send corresponding command type */
writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG);
writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD);
/* Set LBE to send clk at the end of last read block */
if (data) {
mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0x64000000);
} else {
mode &= ~(OWL_SD_CTL_TOUTEN | OWL_SD_CTL_LBE);
mode |= OWL_SD_CTL_TS;
}
owl_host->cmd = cmd;
/* Start transfer */
writel(mode, owl_host->base + OWL_REG_SD_CTL);
if (data)
return;
if (!wait_for_completion_timeout(&owl_host->sdc_complete, 30 * HZ)) {
dev_err(owl_host->dev, "CMD interrupt timeout\n");
cmd->error = -ETIMEDOUT;
return;
}
state = readl(owl_host->base + OWL_REG_SD_STATE);
if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
if (cmd_rsp_mask & state) {
if (state & OWL_SD_STATE_CLNR) {
dev_err(owl_host->dev, "Error CMD_NO_RSP\n");
cmd->error = -EILSEQ;
return;
}
if (state & OWL_SD_STATE_CRC7ER) {
dev_err(owl_host->dev, "Error CMD_RSP_CRC\n");
|