/*
* mmc_spi.c - Access SD/MMC cards through SPI master controllers
*
* (C) Copyright 2005, Intec Automation,
* Mike Lavender (mike@steroidmicros)
* (C) Copyright 2006-2007, David Brownell
* (C) Copyright 2007, Axis Communications,
* Hans-Peter Nilsson (hp@axis.com)
* (C) Copyright 2007, ATRON electronic GmbH,
* Jan Nikitenko <jan.nikitenko@gmail.com>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/hrtimer.h>
#include <linux/delay.h>
#include <linux/bio.h>
#include <linux/dma-mapping.h>
#include <linux/crc7.h>
#include <linux/crc-itu-t.h>
#include <linux/scatterlist.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */
#include <linux/spi/spi.h>
#include <linux/spi/mmc_spi.h>
#include <asm/unaligned.h>
/* NOTES:
*
* - For now, we won't try to interoperate with a real mmc/sd/sdio
* controller, although some of them do have hardware support for
* SPI protocol. The main reason for such configs would be mmc-ish
* cards like DataFlash, which don't support that "native" protocol.
*
* We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to
* switch between driver stacks, and in any case if "native" mode
* is available, it will be faster and hence preferable.
*
* - MMC depends on a different chipselect management policy than the
* SPI interface currently supports for shared bus segments: it needs
* to issue multiple spi_message requests with the chipselect active,
* using the results of one message to decide the next one to issue.
*
* Pending updates to the programming interface, this driver expects
* that it not share the bus with other drivers (precluding conflicts).
*
* - We tell the controller to keep the chipselect active from the
* beginning of an mmc_host_ops.request until the end. So beware
* of SPI controller drivers that mis-handle the cs_change flag!
*
* However, many cards seem OK with chipselect flapping up/down
* during that time ... at least on unshared bus segments.
*/
/*
* Local protocol constants, internal to data block protocols.
*/
/* Response tokens used to ack each block written: */
#define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
#define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
#define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
#define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
/* Read and write blocks start with these tokens and end with crc;
* on error, read tokens act like a subset of R2_SPI_* values.
*/
#define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */
#define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */
#define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */
#define MMC_SPI_BLOCKSIZE 512
/* These fixed timeouts come from the latest SD specs, which say to ignore
* the CSD values. The R1B value is for card erase (e.g. the "I forgot the
* card's password" scenario); it's mostly applied to STOP_TRANSMISSION after
* reads which takes nowhere near that long. Older cards may be able to use
* shorter timeouts ... but why bother?
*/
#define readblock_timeout ktime_set(0, 100 * 1000 * 1000)
#define writeblock_timeout ktime_set(0, 250 * 1000 * 1000)
#define r1b_timeout ktime_set(3, 0)
/****************************************************************************/
/*
* Local Data Structures
*/
/* "scratch" is per-{command,block} data exchanged with the card */
struct scratch {
u8 status[29];
u8 data_token;
__be16 crc_val;
};
struct mmc