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|
/*
* Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
*
* Copyright (C) 2010 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/wait.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/mfd/core.h>
#include <linux/mfd/ti_ssp.h>
/* Register Offsets */
#define REG_REV 0x00
#define REG_IOSEL_1 0x04
#define REG_IOSEL_2 0x08
#define REG_PREDIV 0x0c
#define REG_INTR_ST 0x10
#define REG_INTR_EN 0x14
#define REG_TEST_CTRL 0x18
/* Per port registers */
#define PORT_CFG_2 0x00
#define PORT_ADDR 0x04
#define PORT_DATA 0x08
#define PORT_CFG_1 0x0c
#define PORT_STATE 0x10
#define SSP_PORT_CONFIG_MASK (SSP_EARLY_DIN | SSP_DELAY_DOUT)
#define SSP_PORT_CLKRATE_MASK 0x0f
#define SSP_SEQRAM_WR_EN BIT(4)
#define SSP_SEQRAM_RD_EN BIT(5)
#define SSP_START BIT(15)
#define SSP_BUSY BIT(10)
#define SSP_PORT_ASL BIT(7)
#define SSP_PORT_CFO1 BIT(6)
#define SSP_PORT_SEQRAM_SIZE 32
static const int ssp_port_base[] = {0x040, 0x080};
static const int ssp_port_seqram[] = {0x100, 0x180};
struct ti_ssp {
struct resource *res;
struct device *dev;
void __iomem *regs;
spinlock_t lock;
struct clk *clk;
int irq;
wait_queue_head_t wqh;
/*
* Some of the iosel2 register bits always read-back as 0, we need to
* remember these values so that we don't clobber previously set
* values.
*/
u32 iosel2;
};
static inline struct ti_ssp *dev_to_ssp(struct device *dev)
{
return dev_get_drvdata(dev->parent);
}
static inline int dev_to_port(struct device *dev)
{
return to_platform_device(dev)->id;
}
/* Register Access Helpers, rmw() functions need to run locked */
static inline u32 ssp_read(struct ti_ssp *ssp, int reg)
{
return __raw_readl(ssp->regs + reg);
}
static inline void ssp_write(struct ti_ssp *ssp, int reg, u32 val)
{
__raw_writel(val, ssp->regs + reg);
}
static inline void ssp_rmw(struct ti_ssp *ssp, int reg, u32 mask, u32 bits)
{
ssp_write(ssp, reg, (ssp_read(ssp, reg) & ~mask) | bits);
}
static inline u32 ssp_port_read(struct ti_ssp *ssp, int port, int reg)
{
return ssp_read(ssp, ssp_port_base[port] + reg);
}
static inline void ssp_port_write(struct ti_ssp *ssp, int port, int reg,
u32 val)
{
ssp_write(ssp, ssp_port_base[port] + reg, val);
}
static inline void ssp_port_rmw(struct ti_ssp *ssp, int port, int reg,
u32 mask, u32 bits)
{
ssp_rmw(ssp, ssp_port_base[port] + reg, mask, bits);
}
static inline void ssp_port_clr_bits(struct ti_ssp *ssp, int port, int reg,
u32 bits)
{
ssp_port_rmw(ssp, port, reg, bits, 0);
}
static inline void ssp_port_set_bits(struct ti_ssp *ssp, int port, int reg,
u32 bits)
{
ssp_port_rmw(ssp, port, reg, 0, bits);
}
/* Called to setup port clock mode, caller must hold ssp->lock */
static int __set_mode(struct ti_ssp *ssp, int port, int mode)
{
mode &= SSP_PORT_CONFIG_MASK;
ssp_port_rmw(ssp, port, PORT_CFG_1, SSP_PORT_CONFIG_MASK, mode);
return 0;
}
int ti_ssp_set_mode(struct device *dev, int mode)
{
struct ti_ssp *ssp = dev_to_ssp(dev);
int port = dev_to_port(dev);
int ret;
spin_lock(&ssp->lock);
ret = __set_mode(ssp, port, mode);
spin_unlock(&ssp->lock);
return ret;
}
EXPORT_SYMBOL(ti_ssp_set_mode);
/* Called to setup iosel2, caller must hold ssp->lock */
static void __set_iosel2(struct ti_ssp *ssp, u32 mask, u32 val)
{
ssp->iosel2 = (ssp->iosel2 & ~mask) | val;
ssp_write(ssp, REG_IOSEL_2, ssp->iosel2);
}
/* Called to setup port iosel, caller must hold ssp->lock */
static void __set_iosel(struct ti_ssp *ssp, int port, u32 iosel)
{
unsigned val, shift = port ? 16 : 0;
/* IOSEL1 gets the least significant 16 bits */
val = ssp_read(ssp, REG_IOSEL_1);
val &= 0xffff << (port ? 0 : 16);
val |= (iosel & 0xffff) << (port ? 16 : 0);
ssp_write(ssp, REG_IOSEL_1, val);
/* IOSEL2 gets the most significant 16 bits */
val = (iosel >> 16) & 0x7;
__set_iosel2(ssp, 0x7 << shift, val << shift);
}
int ti_ssp_set_iosel(struct device *dev, u32 iosel)
{
struct ti_ssp *ssp = dev_to_ssp(dev);
int port = dev_to_port(dev);
spin_lock(&ssp->lock);
__set_iosel(ssp, port, iosel);
spin_unlock(&ssp->lock);
return 0;
}
EXPORT_SYMBOL(ti_ssp_set_iosel);
int ti_ssp_load(struct device *dev, int offs, u32* prog, int len)
{
struct ti_ssp *ssp = dev_to_ssp(dev);
int port = dev_to_port(dev);
int i;
if (len > SSP_PORT_SEQRAM_SIZE)
return -ENOSPC;
spin_lock(&ssp->lock);
/* Enable SeqRAM access */
ssp_port_set_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
/* Copy code */
for (i = 0; i < len; i++) {
__raw_writel(prog[i], ssp->regs + offs + 4*i +
ssp_port_seqram[port]);
}
/* Disable SeqRAM access */
ssp_port_clr_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
spin_unlock(&ssp->lock);
return 0;
}
EXPORT_SYMBOL(ti_ssp_load);
int ti_ssp_raw_read(struct device *dev)
{
struct ti_ssp *ssp = dev_to_ssp(dev);
int port = dev_to_port(dev);
int shift = port ? 27 : 11;
return (ssp_read(ssp, REG_IOSEL_2) >> shift) & 0xf;
}
EXPORT_SYMBOL(ti_ssp_raw_read);
int ti_ssp_raw_write(struct device *dev, u32 val)
{
struct ti_ssp *ssp = dev_to_ssp(dev);
int port = dev_to_port(dev), shift;
spin_lock(&ssp->lock);
shift = port ? 22 : 6;
val &= 0xf;
__set_iosel2(ssp, 0xf << shift, val << shift);
spin_unlock(&ssp->lock);
return 0;
}
EXPORT_SYMBOL(ti_ssp_raw_write);
static inline int __xfer_done(struct ti_ssp *ssp, int port)
{
return !(ssp_port_read(ssp, port, PORT_CFG_1) & SSP_BUSY);
}
int ti_ssp_run(
|