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/*
* Toshiba TC6393XB SoC support
*
* Copyright(c) 2005-2006 Chris Humbert
* Copyright(c) 2005 Dirk Opfer
* Copyright(c) 2005 Ian Molton <spyro@f2s.com>
* Copyright(c) 2007 Dmitry Baryshkov
*
* Based on code written by Sharp/Lineo for 2.4 kernels
* Based on locomo.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tmio.h>
#include <linux/mfd/tc6393xb.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#define SCR_REVID 0x08 /* b Revision ID */
#define SCR_ISR 0x50 /* b Interrupt Status */
#define SCR_IMR 0x52 /* b Interrupt Mask */
#define SCR_IRR 0x54 /* b Interrupt Routing */
#define SCR_GPER 0x60 /* w GP Enable */
#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
#define SCR_CCR 0x98 /* w Clock Control */
#define SCR_PLL2CR 0x9a /* w PLL2 Control */
#define SCR_PLL1CR 0x9c /* l PLL1 Control */
#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
#define SCR_FER 0xe0 /* b Function Enable */
#define SCR_MCR 0xe4 /* w Mode Control */
#define SCR_CONFIG 0xfc /* b Configuration Control */
#define SCR_DEBUG 0xff /* b Debug */
#define SCR_CCR_CK32K BIT(0)
#define SCR_CCR_USBCK BIT(1)
#define SCR_CCR_UNK1 BIT(4)
#define SCR_CCR_MCLK_MASK (7 << 8)
#define SCR_CCR_MCLK_OFF (0 << 8)
#define SCR_CCR_MCLK_12 (1 << 8)
#define SCR_CCR_MCLK_24 (2 << 8)
#define SCR_CCR_MCLK_48 (3 << 8)
#define SCR_CCR_HCLK_MASK (3 << 12)
#define SCR_CCR_HCLK_24 (0 << 12)
#define SCR_CCR_HCLK_48 (1 << 12)
#define SCR_FER_USBEN BIT(0) /* USB host enable */
#define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
#define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
#define SCR_MCR_RDY_MASK (3 << 0)
#define SCR_MCR_RDY_OPENDRAIN (0 << 0)
#define SCR_MCR_RDY_TRISTATE (1 << 0)
#define SCR_MCR_RDY_PUSHPULL (2 << 0)
#define SCR_MCR_RDY_UNK BIT(2)
#define SCR_MCR_RDY_EN BIT(3)
#define SCR_MCR_INT_MASK (3 << 4)
#define SCR_MCR_INT_OPENDRAIN (0 << 4)
#define SCR_MCR_INT_TRISTATE (1 << 4)
#define SCR_MCR_INT_PUSHPULL (2 << 4)
#define SCR_MCR_INT_UNK BIT(6)
#define SCR_MCR_INT_EN BIT(7)
/* bits 8 - 16 are unknown */
#define TC_GPIO_BIT(i) (1 << (i & 0x7))
/*--------------------------------------------------------------------------*/
struct tc6393xb {
void __iomem *scr;
struct gpio_chip gpio;
struct clk *clk; /* 3,6 Mhz */
raw_spinlock_t lock; /* protects RMW cycles */
struct {
u8 fer;
u16 ccr;
u8 gpi_bcr[3];
u8 gpo_dsr[3];
u8 gpo_doecr[3];
} suspend_state;
struct resource rscr;
struct resource *iomem;
int irq;
int irq_base;
};
enum {
TC6393XB_CELL_NAND,
TC6393XB_CELL_MMC,
TC6393XB_CELL_OHCI,
TC6393XB_CELL_FB,
};
/*--------------------------------------------------------------------------*/
static int tc6393xb_nand_enable(struct platform_device *nand)
{
struct platform_device *dev = to_platform_device(nand->dev.parent);
struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
unsigned long flags;
raw_spin_lock_irqsave(&tc6393xb->lock, flags);
/* SMD buffer on */
dev_dbg(&dev->dev, "SMD buffer on\n");
tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));
raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
return 0;
}
static struct resource tc6393xb_nand_resources[] = {
{
.start = 0x1000,
.end = 0x1007,
.flags = IORESOURCE_MEM,
},
{
.start = 0x0100,
.end = 0x01ff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_TC6393_NAND,
.end = IRQ_TC6393_NAND,
.flags = IORESOURCE_IRQ,
},
};
static struct resource tc6393xb_mmc_resources[] = {
{
.start = 0x800,
.end = 0x9ff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_TC6393_MMC,
.end = IRQ_TC6393_MMC,
.flags = IORESOURCE_IRQ,
},
};
static const struct resource tc6393xb_ohci_resources[] = {
{
.start = 0x3000,
.end = 0x31ff,
.flags = IORESOURCE_MEM,
},
{
.start = 0x0300,
.end = 0x03ff,
.flags = IORESOURCE_MEM,
},
{
.start = 0x010000,
.end = 0x017fff,
.flags = IORESOURCE_MEM,
},
{
.start = 0x018000,
.end = 0x01ffff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_TC6393_OHCI,
.end = IRQ_TC6393_OHCI,
.flags = IORESOURCE_IRQ,
},
};
static struct resource tc6393xb_fb_resources[] = {
{
.start = 0x5000,
.end = 0x51ff,
.flags = IORESOURCE_MEM,
},
{
.start = 0x0500,
.end = 0x05ff,
.flags = IORESOURCE_MEM,
},
{
.start = 0x100000,
.end = 0x1fffff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_TC6393_FB,
.end = IRQ_TC6393_FB,
.flags = IORESOURCE_IRQ,
},
};
static int tc6393xb_ohci_enable(struct platform_device *dev)
{
struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
unsigned long flags;
u16 ccr;
u8 fer;
raw_spin_lock_irqsave(&tc6393xb->lock, flags);
ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
ccr |= SCR_CCR_USBCK;
tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
fer = tmio_ioread8(tc6393xb->scr + SCR_FER
|