/*
* Driver for the internal tuner of Montage M88RS6000
*
* Copyright (C) 2014 Max nibble <nibble.max@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "m88rs6000t.h"
#include <linux/regmap.h>
struct m88rs6000t_dev {
struct m88rs6000t_config cfg;
struct i2c_client *client;
struct regmap *regmap;
u32 frequency_khz;
};
struct m88rs6000t_reg_val {
u8 reg;
u8 val;
};
/* set demod main mclk and ts mclk */
static int m88rs6000t_set_demod_mclk(struct dvb_frontend *fe)
{
struct m88rs6000t_dev *dev = fe->tuner_priv;
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
u8 reg11, reg15, reg16, reg1D, reg1E, reg1F;
u8 N, f0 = 0, f1 = 0, f2 = 0, f3 = 0;
u16 pll_div_fb;
u32 div, ts_mclk;
unsigned int utmp;
int ret;
/* select demod main mclk */
ret = regmap_read(dev->regmap, 0x15, &utmp);
if (ret)
goto err;
reg15 = utmp;
if (c->symbol_rate > 45010000) {
reg11 = 0x0E;
reg15 |= 0x02;
reg16 = 115; /* mclk = 110.25MHz */
} else {
reg11 = 0x0A;
reg15 &= ~0x02;
reg16 = 96; /* mclk = 96MHz */
}
/* set ts mclk */
if (c->delivery_system == SYS_DVBS)
ts_mclk = 96000;
else
ts_mclk = 144000;
pll_div_fb = (reg15 & 0x01) << 8;
pll_div_fb += reg16;
pll_div_fb += 32;
div = 36000 * pll_div_fb;
div /= ts_mclk;
if (div <= 32) {
N = 2;
f0 = 0;
f1 = div / 2;
f2 = div - f1;
f3 = 0;
} else if (div <= 48) {
N = 3;
f0 = div / 3;
f1 = (div - f0) / 2;
f2 = div - f0 - f1;
f3 = 0;
} else if (div <= 64) {
N = 4;
f0 = div / 4;
f1 = (div - f0) / 3;
f2 = (div - f0 - f1) / 2;
f3 = div - f0 - f1 - f2;
} else {
N = 4;
f0 = 16;
f1 = 16;
f2 = 16;
f3 = 16;
}
if (f0 == 16)
f0 = 0;
if (f1 == 16)
f1 = 0;
if (f2 == 16)
f2 = 0;
if (f3 == 16)
f3 = 0;
ret = regmap_read(dev->regmap, 0x1D, &utmp);
if (ret)
goto err;
reg1D = utmp;
reg1D &= ~0x03;
reg1D |= N - 1;
reg1E = ((f3 << 4) + f2) & 0xFF;
reg1F = ((f1 << 4) + f0) & 0xFF;
/* program and recalibrate demod PLL */
ret = regmap_write(dev->regmap, 0x05, 0x40);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x11, 0x08);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x15, reg15);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x16, reg16);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x1D, reg1D);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x1E, reg1E);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x1F, reg1F);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x17, 0xc1);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x17, 0x81);
if (ret)
goto err;
usleep_range(5000, 50000);
ret = regmap_write(dev->regmap, 0x05, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x11, reg11);
if (ret)
goto err;
usleep_range(5000, 50000);
err:
if (ret)
dev_dbg(&dev->client->dev, "failed=%d\n", ret);
return ret;
}
static int m88rs6000t_set_pll_freq(struct m88rs6000t_dev *dev,
u32 tuner_freq_MHz)
{
u32 fcry_KHz, ulNDiv1, ulNDiv2, ulNDiv;
u8 refDiv, ucLoDiv1, ucLomod1,