// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Elonics E4000 silicon tuner driver
*
* Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
*/
#include "e4000_priv.h"
static int e4000_init(struct e4000_dev *dev)
{
struct i2c_client *client = dev->client;
int ret;
dev_dbg(&client->dev, "\n");
/* reset */
ret = regmap_write(dev->regmap, 0x00, 0x01);
if (ret)
goto err;
/* disable output clock */
ret = regmap_write(dev->regmap, 0x06, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x7a, 0x96);
if (ret)
goto err;
/* configure gains */
ret = regmap_bulk_write(dev->regmap, 0x7e, "\x01\xfe", 2);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x82, 0x00);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x24, 0x05);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x87, "\x20\x01", 2);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x9f, "\x7f\x07", 2);
if (ret)
goto err;
/* DC offset control */
ret = regmap_write(dev->regmap, 0x2d, 0x1f);
if (ret)
goto err;
ret = regmap_bulk_write(dev->regmap, 0x70, "\x01\x01", 2);
if (ret)
goto err;
/* gain control */
ret = regmap_write(dev->regmap, 0x1a, 0x17);
if (ret)
goto err;
ret = regmap_write(dev->regmap, 0x1f, 0x1a);
if (ret)
goto err;
dev->active = true;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int e4000_sleep(struct e4000_dev *dev)
{
struct i2c_client *client = dev->client;
int ret;
dev_dbg(&client->dev, "\n");
dev->active = false;
ret = regmap_write(dev->regmap, 0x00, 0x00);
if (ret)
goto err;
return 0;
err:
dev_dbg(&client->dev, "failed=%d\n", ret);
return ret;
}
static int e4000_set_params(struct e4000_dev *dev)
{
struct i2c_client *client = dev->client;
int ret, i;
unsigned int div_n, k, k_cw, div_out;
u64 f_vco;
u8 buf[5], i_data[4], q_data[4];
if (!dev->active) {
dev_dbg(&client->dev, "tuner is sleeping\n");
return 0;
}
/* gain control manual */
ret = regmap_write(dev->regmap, 0x1a, 0x00);
if (ret)
goto err;
/*
* Fractional-N synthesizer
*
* +----------------------------+
* v |
* Fref +----+ +-------+ +------+ +---+
* ------> | PD | --> | VCO | ------> | /N.F | <-- | K |
* +----+ +-------+ +------+ +---+
* |
* |
* v
* +-------+ Fout
* | /Rout | ------>
* +-------+
*/
for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
if (dev->f_frequency <= e4000_pll_lut[i].freq)
break;
}
if (i == ARRAY_SIZE(e4000_pll_lut)) {
ret = -EINVAL;
goto err;
}
#define F_REF dev->clk
div_out = e4000_pll_lut[i].div_out;
f_vco = (u64) dev->f_frequency * div_out;
/* calculate PLL integer and fractional control word */
div_n = div_u64_rem(f_vco, F_REF, &k);
k_cw = div_u64((u64) k * 0x10000, F_REF);
dev_dbg(&client->dev,
"frequency=%u bandwidth=%u f_vco=%llu F_REF=%u div_n=%u k=%u k_cw=%04x div_out=%u\n",
dev->f_frequency, dev->f_bandwidth, f_vco, F_REF, div_n, k,
k_cw, div_out);
buf[0] = div_n;
buf[1] = (k_cw >> 0) & 0xff;
buf[2] = (k_cw >> 8) & 0xff;
buf[3] = 0x00;
buf[4] = e4000_pll_lut[i].div_out_reg;
ret = regmap_bulk_write(dev->regmap, 0x09, buf, 5);
if (ret)
goto err;
/* LNA filter (RF filter) */
for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) {
if (dev->f_frequency <= e400_lna_filter_lut[i].freq)
break;
}
if (i == ARRAY_SIZE(e400_lna_filter_lut)) {
ret = -EINVAL;
goto err;
}
ret = regmap_write(dev->regmap, 0x10, e400_lna_filter_lut[i].val);
if (ret)
goto err;
/* IF filters */
for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) {
if (dev->f_bandwidth <= e4000_if_filter_lut[i].freq)
break;
}
if (i == ARRAY_SIZE(e4000_if_filter_lut)) {
ret =