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|
// SPDX-License-Identifier: GPL-2.0
/*
* camss-vfe-4-1.c
*
* Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.1
*
* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
* Copyright (C) 2015-2018 Linaro Ltd.
*/
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include "camss-vfe.h"
#define VFE_0_HW_VERSION 0x000
#define VFE_0_GLOBAL_RESET_CMD 0x00c
#define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0)
#define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1)
#define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2)
#define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3)
#define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4)
#define VFE_0_GLOBAL_RESET_CMD_TIMER BIT(5)
#define VFE_0_GLOBAL_RESET_CMD_PM BIT(6)
#define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(7)
#define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(8)
#define VFE_0_MODULE_CFG 0x018
#define VFE_0_MODULE_CFG_DEMUX BIT(2)
#define VFE_0_MODULE_CFG_CHROMA_UPSAMPLE BIT(3)
#define VFE_0_MODULE_CFG_SCALE_ENC BIT(23)
#define VFE_0_MODULE_CFG_CROP_ENC BIT(27)
#define VFE_0_CORE_CFG 0x01c
#define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4
#define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5
#define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6
#define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7
#define VFE_0_IRQ_CMD 0x024
#define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0)
#define VFE_0_IRQ_MASK_0 0x028
#define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0)
#define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1)
#define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5)
#define VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(n) \
((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n))
#define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8)
#define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25)
#define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31)
#define VFE_0_IRQ_MASK_1 0x02c
#define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0)
#define VFE_0_IRQ_MASK_1_VIOLATION BIT(7)
#define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8)
#define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9)
#define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29)
#define VFE_0_IRQ_CLEAR_0 0x030
#define VFE_0_IRQ_CLEAR_1 0x034
#define VFE_0_IRQ_STATUS_0 0x038
#define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0)
#define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5)
#define VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(n) \
((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n))
#define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8)
#define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25)
#define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31)
#define VFE_0_IRQ_STATUS_1 0x03c
#define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7)
#define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8)
#define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29)
#define VFE_0_IRQ_COMPOSITE_MASK_0 0x40
#define VFE_0_VIOLATION_STATUS 0x48
#define VFE_0_BUS_CMD 0x4c
#define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x)
#define VFE_0_BUS_CFG 0x050
#define VFE_0_BUS_XBAR_CFG_x(x) (0x58 + 0x4 * ((x) / 2))
#define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(1)
#define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA (0x3 << 4)
#define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT 8
#define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA 0
#define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 5
#define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 6
#define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 7
#define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n) (0x06c + 0x24 * (n))
#define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT 0
#define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT 1
#define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n) (0x070 + 0x24 * (n))
#define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n) (0x074 + 0x24 * (n))
#define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n) (0x078 + 0x24 * (n))
#define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT 2
#define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK (0x1f << 2)
#define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n) (0x07c + 0x24 * (n))
#define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT 16
#define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n) (0x080 + 0x24 * (n))
#define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n) (0x084 + 0x24 * (n))
#define VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(n) \
(0x088 + 0x24 * (n))
#define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(n) \
(0x08c + 0x24 * (n))
#define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF 0xffffffff
#define VFE_0_BUS_PING_PONG_STATUS 0x268
#define VFE_0_BUS_BDG_CMD 0x2c0
#define VFE_0_BUS_BDG_CMD_HALT_REQ 1
#define VFE_0_BUS_BDG_QOS_CFG_0 0x2c4
#define VFE_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5
#define VFE_0_BUS_BDG_QOS_CFG_1 0x2c8
#define VFE_0_BUS_BDG_QOS_CFG_2 0x2cc
#define VFE_0_BUS_BDG_QOS_CFG_3 0x2d0
#define VFE_0_BUS_BDG_QOS_CFG_4 0x2d4
#define VFE_0_BUS_BDG_QOS_CFG_5 0x2d8
#define VFE_0_BUS_BDG_QOS_CFG_6 0x2dc
#define VFE_0_BUS_BDG_QOS_CFG_7 0x2e0
#define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa5
#define VFE_0_RDI_CFG_x(x) (0x2e8 + (0x4 * (x)))
#define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28
#define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28)
#define VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT 4
#define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK (0xf << 4)
#define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2)
#define VFE_0_RDI_CFG_x_MIPI_EN_BITS 0x3
#define VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(r) BIT(16 + (r))
#define VFE_0_CAMIF_CMD 0x2f4
#define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY 0
#define VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY 1
#define VFE_0_CAMIF_CMD_NO_CHANGE 3
#define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2)
#define VFE_0_CAMIF_CFG 0x2f8
#define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6)
#define VFE_0_CAMIF_FRAME_CFG 0x300
#define VFE_0_CAMIF_WINDOW_WIDTH_CFG 0x304
#define VFE_0_CAMIF_WINDOW_HEIGHT_CFG 0x308
#define VFE_0_CAMIF_SUBSAMPLE_CFG_0 0x30c
#define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN 0x314
#define VFE_0_CAMIF_STATUS 0x31c
#define VFE_0_CAMIF_STATUS_HALT BIT(31)
#define VFE_0_REG_UPDATE 0x378
#define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n))
#define VFE_0_REG_UPDATE_line_n(n) \
((n) == VFE_LINE_PIX ? 1 : VFE_0_REG_UPDATE_RDIn(n))
#define VFE_0_DEMUX_CFG 0x424
#define VFE_0_DEMUX_CFG_PERIOD 0x3
#define VFE_0_DEMUX_GAIN_0 0x428
#define VFE_0_DEMUX_GAIN_0_CH0_EVEN (0x80 << 0)
#define VFE_0_DEMUX_GAIN_0_CH0_ODD (0x80 << 16)
#define VFE_0_DEMUX_GAIN_1 0x42c
#define VFE_0_DEMUX_GAIN_1_CH1 (0x80 << 0)
#define VFE_0_DEMUX_GAIN_1_CH2 (0x80 << 16)
#define VFE_0_DEMUX_EVEN_CFG 0x438
#define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV 0x9cac
#define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU 0xac9c
#define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY 0xc9ca
#define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY 0xcac9
#define VFE_0_DEMUX_ODD_CFG 0x43c
#define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV 0x9cac
#define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU 0xac9c
#define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca
#define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9
#define VFE_0_SCALE_ENC_Y_CFG 0x75c
#define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x760
#define VFE_0_SCALE_ENC_Y_H_PHASE 0x764
#define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x76c
#define VFE_0_SCALE_ENC_Y_V_PHASE 0x770
#define VFE_0_SCALE_ENC_CBCR_CFG 0x778
#define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x77c
#define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x780
#define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x790
#define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x794
#define VFE_0_CROP_ENC_Y_WIDTH 0x854
#define VFE_0_CROP_ENC_Y_HEIGHT 0x858
#define VFE_0_CROP_ENC_CBCR_WIDTH 0x85c
#define VFE_0_CROP_ENC_CBCR_HEIGHT 0x860
#define VFE_0_CLAMP_ENC_MAX_CFG 0x874
#define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0)
#define VFE_0_CLAMP_ENC_MAX_CFG_CH1 (0xff << 8)
#define VFE_0_CLAMP_ENC_MAX_CFG_CH2 (0xff << 16)
#define VFE_0_CLAMP_ENC_MIN_CFG 0x878
#define VFE_0_CLAMP_ENC_MIN_CFG_CH0 (0x0 << 0)
#define VFE_0_CLAMP_ENC_MIN_CFG_CH1 (0x0 << 8)
#define VFE_0_CLAMP_ENC_MIN_CFG_CH2 (0x0 << 16)
#define VFE_0_CGC_OVERRIDE_1 0x974
#define VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(x) BIT(x)
#define CAMIF_TIMEOUT_SLEEP_US 1000
#define CAMIF_TIMEOUT_ALL_US 1000000
#define MSM_VFE_VFE0_UB_SIZE 1023
#define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3)
static void vfe_hw_version_read(struct vfe_device *vfe, struct device *dev)
{
u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION);
dev_dbg(dev, "VFE HW Version = 0x%08x\n", hw_version);
}
static u16 vfe_get_ub_size(u8 vfe_id)
{
if (vfe_id == 0)
return MSM_VFE_VFE0_UB_SIZE_RDI;
return 0;
}
static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits)
{
u32 bits = readl_relaxed(vfe->base + reg);
writel_relaxed(bits & ~clr_bits, vfe->base + reg);
}
static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits)
{
u32 bits = readl_relaxed(vfe->base + reg);
writel_relaxed(bits | set_bits, vfe->base + reg);
}
static void vfe_global_reset(struct vfe_device *vfe)
{
u32 reset_bits = VFE_0_GLOBAL_RESET_CMD_TESTGEN |
VFE_0_GLOBAL_RESET_CMD_BUS_MISR |
VFE_0_GLOBAL_RESET_CMD_PM |
VFE_0_GLOBAL_RESET_CMD_TIMER |
VFE_0_GLOBAL_RESET_CMD_REGISTER |
VFE_0_GLOBAL_RESET_CMD_BUS_BDG |
VFE_0_GLOBAL_RESET_CMD_BUS |
VFE_0_GLOBAL_RESET_CMD_CAMIF |
VFE_0_GLOBAL_RESET_CMD_CORE;
writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD);
}
static void vfe_halt_request(struct vfe_device *vfe)
{
writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ,
vfe->base + VFE_0_BUS_BDG_CMD);
}
static void vfe_halt_clear(struct vfe_device *vfe)
{
writel_relaxed(
|