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/*
* Driver for SiliconFile SR030PC30 VGA (1/10-Inch) Image Sensor with ISP
*
* Copyright (C) 2010 Samsung Electronics Co., Ltd
* Author: Sylwester Nawrocki, s.nawrocki@samsung.com
*
* Based on original driver authored by Dongsoo Nathaniel Kim
* and HeungJun Kim <riverful.kim@samsung.com>.
*
* Based on mt9v011 Micron Digital Image Sensor driver
* Copyright (c) 2009 Mauro Carvalho Chehab (mchehab@redhat.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
#include <media/v4l2-mediabus.h>
#include <media/v4l2-ctrls.h>
#include <media/sr030pc30.h>
static int debug;
module_param(debug, int, 0644);
#define MODULE_NAME "SR030PC30"
/*
* Register offsets within a page
* b15..b8 - page id, b7..b0 - register address
*/
#define POWER_CTRL_REG 0x0001
#define PAGEMODE_REG 0x03
#define DEVICE_ID_REG 0x0004
#define NOON010PC30_ID 0x86
#define SR030PC30_ID 0x8C
#define VDO_CTL1_REG 0x0010
#define SUBSAMPL_NONE_VGA 0
#define SUBSAMPL_QVGA 0x10
#define SUBSAMPL_QQVGA 0x20
#define VDO_CTL2_REG 0x0011
#define SYNC_CTL_REG 0x0012
#define WIN_ROWH_REG 0x0020
#define WIN_ROWL_REG 0x0021
#define WIN_COLH_REG 0x0022
#define WIN_COLL_REG 0x0023
#define WIN_HEIGHTH_REG 0x0024
#define WIN_HEIGHTL_REG 0x0025
#define WIN_WIDTHH_REG 0x0026
#define WIN_WIDTHL_REG 0x0027
#define HBLANKH_REG 0x0040
#define HBLANKL_REG 0x0041
#define VSYNCH_REG 0x0042
#define VSYNCL_REG 0x0043
/* page 10 */
#define ISP_CTL_REG(n) (0x1010 + (n))
#define YOFS_REG 0x1040
#define DARK_YOFS_REG 0x1041
#define AG_ABRTH_REG 0x1050
#define SAT_CTL_REG 0x1060
#define BSAT_REG 0x1061
#define RSAT_REG 0x1062
#define AG_SAT_TH_REG 0x1063
/* page 11 */
#define ZLPF_CTRL_REG 0x1110
#define ZLPF_CTRL2_REG 0x1112
#define ZLPF_AGH_THR_REG 0x1121
#define ZLPF_THR_REG 0x1160
#define ZLPF_DYN_THR_REG 0x1160
/* page 12 */
#define YCLPF_CTL1_REG 0x1240
#define YCLPF_CTL2_REG 0x1241
#define YCLPF_THR_REG 0x1250
#define BLPF_CTL_REG 0x1270
#define BLPF_THR1_REG 0x1274
#define BLPF_THR2_REG 0x1275
/* page 14 - Lens Shading Compensation */
#define LENS_CTRL_REG 0x1410
#define LENS_XCEN_REG 0x1420
#define LENS_YCEN_REG 0x1421
#define LENS_R_COMP_REG 0x1422
#define LENS_G_COMP_REG 0x1423
#define LENS_B_COMP_REG 0x1424
/* page 15 - Color correction */
#define CMC_CTL_REG 0x1510
#define CMC_OFSGH_REG 0x1514
#define CMC_OFSGL_REG 0x1516
#define CMC_SIGN_REG 0x1517
/* Color correction coefficients */
#define CMC_COEF_REG(n) (0x1530 + (n))
/* Color correction offset coefficients */
#define CMC_OFS_REG(n) (0x1540 + (n))
/* page 16 - Gamma correction */
#define GMA_CTL_REG 0x1610
/* Gamma correction coefficients 0.14 */
#define GMA_COEF_REG(n) (0x1630 + (n))
/* page 20 - Auto Exposure */
#define AE_CTL1_REG 0x2010
#define AE_CTL2_REG 0x2011
#define AE_FRM_CTL_REG 0x2020
#define AE_FINE_CTL_REG(n) (0x2028 + (n))
#define EXP_TIMEH_REG 0x2083
#define EXP_TIMEM_REG 0x2084
#define EXP_TIMEL_REG 0x2085
#define EXP_MMINH_REG 0x2086
#define EXP_MMINL_REG 0x2087
#define EXP_MMAXH_REG 0x2088
#define EXP_MMAXM_REG 0x2089
#define EXP_MMAXL_REG 0x208A
/* page 22 - Auto White Balance */
#define AWB_CTL1_REG 0x2210
#define AWB_ENABLE 0x80
#define AWB_CTL2_REG 0x2211
#define MWB_ENABLE 0x01
/* RGB gain control (manual WB) when AWB_CTL1[7]=0 */
#define AWB_RGAIN_REG 0x2280
#define AWB_GGAIN_REG 0x2281
#define AWB_BGAIN_REG 0x2282
#define AWB_RMAX_REG 0x2283
#define AWB_RMIN_REG 0x2284
#define AWB_BMAX_REG 0x2285
#define AWB_BMIN_REG 0x2286
/* R, B gain range in bright light conditions */
#define AWB_RMAXB_REG 0x2287
#define AWB_RMINB_REG 0x2288
#define AWB_BMAXB_REG 0x2289
#define AWB_BMINB_REG 0x228A
/* manual white balance, when AWB_CTL2[0]=1 */
#define MWB_RGAIN_REG 0x22B2
#define MWB_BGAIN_REG 0x22B3
/* the token to mark an array end */
#define REG_TERM 0xFFFF
/* Minimum and maximum exposure time in ms */
#define EXPOS_MIN_MS 1
#define EXPOS_MAX_MS 125
struct sr030pc30_info {
struct v4l2_subdev sd;
struct v4l2_ctrl_handler hdl;
const struct sr030pc30_platform_data *pdata;
const struct sr030pc30_format *curr_fmt;
const struct sr030pc30_frmsize *curr_win;
unsigned int hflip:1;
unsigned int vflip:1;
unsigned int sleep:1;
struct {
/* auto whitebalance control cluster */
struct v4l2_ctrl *awb;
struct v4l2_ctrl *red;
struct v4l2_ctrl *blue;
};
struct {
/* auto exposure control cluster */
struct v4l2_ctrl *autoexp;
struct v4l2_ctrl *exp;
};
u8 i2c_reg_page;
};
struct sr030pc30_format {
enum v4l2_mbus_pixelcode code;
enum v4l2_colorspace colorspace;
u16 ispctl1_reg;
};
struct sr030pc30_frmsize {
u16 width;
u16 height;
int vid_ctl1;
};
struct i2c_regval {
u16 addr;
u16 val;
};
/* supported resolutions */
static const struct sr030pc30_frmsize sr030pc30_sizes[] = {
{
.width = 640,
.height = 480,
.vid_ctl1 = SUBSAMPL_NONE_VGA,
}, {
.width = 320,
.height = 240,
.vid_ctl1 = SUBSAMPL_QVGA,
}, {
.width = 160,
.height = 120,
.vid_ctl1 = SUBSAMPL_QQVGA,
},
};
/* supported pixel formats */
static const struct sr030pc30_format sr030pc30_formats[] = {
{
.code = V4L2_MBUS_FMT_YUYV8_2X8,
.colorspace = V4L2_COLORSPACE_JPEG,
.ispctl1_reg = 0x03,
}, {
.code = V4L2_MBUS_FMT_YVYU8_2X8,
.colorspace = V4L2_COLORSPACE_JPEG,
.ispctl1_reg = 0x02,
}, {
.code = V4L2_MBUS_FMT_VYUY8_2X8,
.colorspace = V4L2_COLORSPACE_JPEG,
.ispctl1_reg = 0,
}, {
.code = V4L2_MBUS_FMT_UYVY8_2X8,
.colorspace = V4L2_COLORSPACE_JPEG,
.ispctl1_reg = 0x01,
}, {
.code = V4L2_MBUS_FMT_RGB565_2X8_BE,
.colorspace = V4L2_COLORSPACE_JPEG,
.ispctl1_reg = 0x40,
},
};
static const struct i2c_regval sr030pc30_base_regs[] = {
/* Window size and position within pixel matrix */
{ WIN_ROWH_REG, 0x00 }, { WIN_ROWL_REG, 0x06 },
{ WIN_COLH_REG, 0x00 }, { WIN_COLL_REG, 0x06 },
{ WIN_HEIGHTH_REG, 0x01 }, { WIN_HEIGHTL_REG, 0xE0 },
{ WIN_WIDTHH_REG, 0x02 }, { WIN_WIDTHL_REG, 0x80 },
{ HBLANKH_REG, 0x01 }, { HBLANKL_REG, 0x50 },
{ VSYNCH_REG, 0x00 }, { VSYNCL_REG, 0x14 },
{ SYNC_CTL_REG, 0 },
/* Color corection and saturation */
{ ISP_CTL_REG(0), 0x30 }, { YOFS_REG, 0x80 },
{ DARK_YOFS_REG, 0x04 }, { AG_ABRTH_REG, 0x78 },
{ SAT_CTL_REG, 0x1F }, { BSAT_REG, 0x90 },
{ AG_SAT_TH_REG, 0xF0 }, { 0x1064, 0x80 },
{ CMC_CTL_REG, 0x03 }, { CMC_OFSGH_REG, 0x3C },
{ CMC_OFSGL_REG, 0x2C }, { CMC_SIGN_REG, 0x2F },
{ CMC_COEF_REG(0), 0xCB }, { CMC_OFS_REG(0), 0x87 },
{ CMC_COEF_REG(1), 0x61 }, { CMC_OFS_REG(1), 0x18 },
{ CMC_COEF_REG(2), 0x16 }, { CMC_OFS_REG(2), 0x91 },
{ CMC_COEF_REG(3), 0x23 }, { CMC_OFS_REG(3), 0x94 },
{ CMC_COEF_REG(4), 0xCE }, { CMC_OFS_REG(4), 0x9f },
{ CMC_COEF_REG(5), 0x2B }, { CMC_OFS_REG(5), 0x33 },
{ CMC_COEF_REG(6), 0x01 },
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