1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
#define IMX_MU_xSR_BRDIP BIT(9)
/* General Purpose Interrupt Enable */
#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
/* Receive Interrupt Enable */
#define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
/* Transmit Interrupt Enable */
#define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
/* General Purpose Interrupt Request */
#define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
#define IMX_MU_CHANS 16
#define IMX_MU_CHAN_NAME_SIZE 20
enum imx_mu_chan_type {
IMX_MU_TYPE_TX, /* Tx */
IMX_MU_TYPE_RX, /* Rx */
IMX_MU_TYPE_TXDB, /* Tx doorbell */
IMX_MU_TYPE_RXDB, /* Rx doorbell */
};
struct imx_mu_dcfg {
u32 xTR[4]; /* Transmit Registers */
u32 xRR[4]; /* Receive Registers */
u32 xSR; /* Status Register */
u32 xCR; /* Control Register */
};
struct imx_mu_con_priv {
unsigned int idx;
char irq_desc[IMX_MU_CHAN_NAME_SIZE];
enum imx_mu_chan_type type;
struct mbox_chan *chan;
struct tasklet_struct txdb_tasklet;
};
struct imx_mu_priv {
struct device *dev;
void __iomem *base;
spinlock_t xcr_lock; /* control register lock */
struct mbox_controller mbox;
struct mbox_chan mbox_chans[IMX_MU_CHANS];
struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
const struct imx_mu_dcfg *dcfg;
struct clk *clk;
int irq;
bool side_b;
};
static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
.xTR = {0x0, 0x4, 0x8, 0xc},
.xRR = {0x10, 0x14, 0x18, 0x1c},
.xSR = 0x20,
.xCR = 0x24,
};
static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
.xTR = {0x20, 0x24, 0x28, 0x2c},
.xRR = {0x40, 0x44, 0x48, 0x4c},
.xSR = 0x60,
.xCR = 0x64,
};
static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
{
return container_of(mbox, struct imx_mu_priv, mbox);
}
static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
{
iowrite32(val, priv->base + offs);
}
static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
{
return ioread32(priv->base + offs);
}
static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&priv->xcr_lock, flags);
val = imx_mu_read(priv, priv->dcfg->xCR);
val &= ~clr;
val |= set;
imx_mu_write(priv, val, priv->dcfg->xCR);
spin_unlock_irqrestore(&priv->xcr_lock, flags);
return val;
}
static void imx_mu_txdb_tasklet(unsigned long data)
{
struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
mbox_chan_txdone(cp->chan, 0);
}
static irqreturn_t imx_mu_isr(int irq, void *p)
{
struct mbox_chan *chan = p;
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
struct imx_mu_con_priv *cp = chan->con_priv;
u32 val, ctrl, dat;
ctrl = imx_mu_read(priv, priv->dcfg->xCR);
val = imx_mu_read(priv, priv->dcfg->xSR);
switch (cp->type) {
case IMX_MU_TYPE_TX:
val &= IMX_MU_xSR_TEn(cp->idx) &
(ctrl & IMX_MU_xCR_TIEn(cp->idx));
break;
case IMX_MU_TYPE_RX:
val &= IMX_MU_xSR_RFn(cp->idx) &
(ctrl & IMX_MU_xCR_RIEn(cp->idx));
break;
case IMX_MU_TYPE_RXDB:
val &= IMX_MU_xSR_GIPn(cp->idx) &
(ctrl & IMX_MU_xCR_GIEn(cp->idx));
break;
default:
break;
}
if (!val)
return IRQ_NONE;
if (val == IMX_MU_xSR_TEn(cp->idx)) {
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
mbox_chan_txdone(chan, 0);
} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
mbox_chan_received_data(chan, (void *)&dat);
} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
mbox_chan_received_data(chan, NULL);
} else {
dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
return IRQ_NONE;
}
return IRQ_HANDLED;
}
static int imx_mu_send_data(struct mbox_chan *chan, void *data)
{
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
struct imx_mu_con_priv *cp = chan->con_priv;
u32 *arg = data;
switch (cp->type) {
case IMX_MU_TYPE_TX:
imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
break;
case IMX_MU_TYPE_TXDB:
imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
tasklet_schedule(&cp->txdb_tasklet);
break;
default:
dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
return -EINVAL;
}
return 0;
}
static int imx_mu_startup(struct mbox_chan *chan)
{
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
struct imx_mu_con_priv *cp = chan->con_priv;
int ret;
if (cp->type == IMX_MU_TYPE_TXDB) {
/* Tx doorbell don't have ACK support */
tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
(unsigned long)cp);
return 0;
}
ret = request_irq(priv->irq, imx_mu_isr, IRQF_SHARED |
IRQF_NO_SUSPEND, cp->irq_desc, chan);
if (ret) {
dev_err(priv->dev,
"Unable to acquire IRQ %d\n", priv->irq);
return ret;
}
switch (cp->type) {
case IMX_MU_TYPE_RX:
imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
break;
case IMX_MU_TYPE_RXDB:
imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
break;
default:
break;
}
return 0;
}
static void imx_mu_shutdown(struct mbox_chan *chan)
{
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
struct imx_mu_con_priv *cp = chan->con_priv;
if (cp->type == IMX_MU_TYPE_TXDB) {
tasklet_kill(&cp->txdb_tasklet);
return;
}
switch (cp->type) {
case IMX_MU_TYPE_TX:
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
break;
case IMX_MU_TYPE_RX:
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
break;
case IMX_MU_TYPE_RXDB:
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
break;
default:
break;
}
free_irq(priv->irq, chan);
}
static const struct mbox_chan_ops imx_mu_ops = {
.send_data = imx_mu_send_data,
.startup
|