1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
|
/*
* Broadcom BCM6345 style Level 1 interrupt controller driver
*
* Copyright (C) 2014 Broadcom Corporation
* Copyright 2015 Simon Arlott
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This is based on the BCM7038 (which supports SMP) but with a single
* enable register instead of separate mask/set/clear registers.
*
* The BCM3380 has a similar mask/status register layout, but each pair
* of words is at separate locations (and SMP is not supported).
*
* ENABLE/STATUS words are packed next to each other for each CPU:
*
* BCM6368:
* 0x1000_0020: CPU0_W0_ENABLE
* 0x1000_0024: CPU0_W1_ENABLE
* 0x1000_0028: CPU0_W0_STATUS IRQs 31-63
* 0x1000_002c: CPU0_W1_STATUS IRQs 0-31
* 0x1000_0030: CPU1_W0_ENABLE
* 0x1000_0034: CPU1_W1_ENABLE
* 0x1000_0038: CPU1_W0_STATUS IRQs 31-63
* 0x1000_003c: CPU1_W1_STATUS IRQs 0-31
*
* BCM63168:
* 0x1000_0020: CPU0_W0_ENABLE
* 0x1000_0024: CPU0_W1_ENABLE
* 0x1000_0028: CPU0_W2_ENABLE
* 0x1000_002c: CPU0_W3_ENABLE
* 0x1000_0030: CPU0_W0_STATUS IRQs 96-127
* 0x1000_0034: CPU0_W1_STATUS IRQs 64-95
* 0x1000_0038: CPU0_W2_STATUS IRQs 32-63
* 0x1000_003c: CPU0_W3_STATUS IRQs 0-31
* 0x1000_0040: CPU1_W0_ENABLE
* 0x1000_0044: CPU1_W1_ENABLE
* 0x1000_0048: CPU1_W2_ENABLE
* 0x1000_004c: CPU1_W3_ENABLE
* 0x1000_0050: CPU1_W0_STATUS IRQs 96-127
* 0x1000_0054: CPU1_W1_STATUS IRQs 64-95
* 0x1000_0058: CPU1_W2_STATUS IRQs 32-63
* 0x1000_005c: CPU1_W3_STATUS IRQs 0-31
*
* IRQs are numbered in CPU native endian order
* (which is big-endian in these examples)
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bitops.h>
#include <linux/cpumask.h>
#include <linux/kconfig.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/smp.h>
#include <linux/types.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>
#define IRQS_PER_WORD 32
#define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 2)
struct bcm6345_l1_cpu;
struct bcm6345_l1_chip {
raw_spinlock_t lock;
unsigned int n_words;
struct irq_domain *domain;
struct cpumask cpumask;
struct bcm6345_l1_cpu *cpus[NR_CPUS];
};
struct bcm6345_l1_cpu {
void __iomem *map_base;
unsigned int parent_irq;
u32 enable_cache[];
};
static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc,
unsigned int word)
{
#ifdef __BIG_ENDIAN
return (1 * intc->n_words - word - 1) * sizeof(u32);
#else
return (0 * intc->n_words + word) * sizeof(u32);
#endif
}
static inline unsigned int reg_status(struct bcm6345_l1_chip *intc,
unsigned int word)
{
#ifdef __BIG_ENDIAN
return (2 * intc->n_words - word - 1) * sizeof(u32);
#else
return (1 * intc->n_words + word) * sizeof(u32);
#endif
}
static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc,
struct irq_data *d)
{
return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d));
}
static void bcm6345_l1_irq_handle(struct irq_desc *desc)
{
struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc);
struct bcm6345_l1_cpu *cpu;
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int idx;
#ifdef CONFIG_SMP
cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
#else
cpu = intc->cpus[0];
#endif
chained_irq_enter(chip, desc);
for (idx = 0; idx < intc->n_words; idx++) {
int base = idx * IRQS_PER_WORD;
unsigned long pending;
irq_hw_number_t hwirq;
unsigned int irq;
pending = __raw_readl(cpu->map_base + reg_status(intc, idx));
pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));
for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
irq = irq_linear_revmap(intc->domain, base + hwirq);
if (irq)
do_IRQ(irq);
else
spurious_interrupt();
}
}
chained_irq_exit(chip, desc);
}
static inline void __bcm6345_l1_unmask(struct irq_data *d)
{
struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
u32 word = d->hwirq / IRQS_PER_WORD;
u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
unsigned int cpu_idx = cpu_for_irq(intc, d);
intc->cpus[cpu_idx]->enable_cache[word] |= mask;
__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
}
static inline void __bcm6345_l1_mask(struct irq_data *d)
{
struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
u32 word = d->hwirq / IRQS_PER_WORD;
u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
unsigned int cpu_idx = cpu_for_irq(intc, d);
intc->cpus[cpu_idx]->enable_cache[word] &= ~mask;
__raw_writel(intc->cpus[cpu_idx]->enable_cache[word],
intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
}
static void bcm6345_l1_unmask(struct irq_data *d)
{
struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
unsigned long flags;
raw_spin_lock_irqsave(&intc->lock, flags);
__bcm6345_l1_unmask(d);
raw_spin_unlock_irqrestore(&intc->lock, flags);
}
static void bcm6345_l1_mask(struct irq_data *d)
{
struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
unsigned long flags;
raw_spin_lock_irqsave(&intc->lock, flags);
__bcm6345_l1_mask(d);
raw_spin_unlock_irqrestore(&intc->lock, flags);
}
static int bcm6345_l1_set_affinity(struct irq_data *d,
const struct cpumask *dest,
bool force)
{
struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d);
u32 word = d->hwirq / IRQS_PER_WORD;
u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
unsigned int old_cpu = cpu_for_irq(intc, d);
unsigned int new_cpu;
struct cpumask valid;
unsigned long flags;
bool enabled;
if (!cpumask_and(&valid, &intc->cpumask, dest))
return -EINVAL;
new_cpu = cpumask_any_and(&valid, cpu_online_mask);
if (new_cpu >= nr_cpu_ids)
return -EINVAL;
dest = cpumask_of(new_cpu);
raw_spin_lock_irqsave(&intc->lock, flags);
if (old_cpu != new_cpu) {
enabled = intc->cpus[old_cpu]->enable_cache[word] & mask;
if (enabled)
__bcm6345_l1_mask(d);
cpumask_copy(irq_data_get_affinity_mask(d), dest);
if (enabled)
__bcm6345_l1_unmask(d);
} else {
cpumask_copy(irq_data_get_affinity_mask(d), dest);
}
raw_spin_unlock_irqrestore(&intc->lock, flags);
return IRQ_SET_MASK_OK_NOCOPY;
}
static int __init bcm6345_l1_init_one(struct device_node *dn,
unsigned int idx,
struct bcm6345_l1_chip *intc)
{
struct resource res;
resource_size_t sz;
struct bcm6345_l1_cpu *cpu;
unsigned int i, n_words;
if (of_address_to_resource(dn, idx, &res))
return -EINVAL;
sz = resource_size(&res);
n_words = sz / REG_BYTES_PER_IRQ_WORD;
if (!intc->n_words)
intc->n_words = n_words;
else if (intc->n_words != n_words)
return -EINVAL;
cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
GFP_KERNEL);
if (!cpu)
return -ENOMEM;
cpu->map_base = ioremap(res.start, sz);
if (!cpu->map_base)
return -ENOMEM;
for (i = 0; i < n_words; i++) {
cpu->enable_cache[i] = 0;
__raw_writel(0, cpu->map_base + reg_enable(intc, i));
}
cpu->parent_irq = irq_of_parse_and_map(dn, idx);
|