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|
/*
* CPU-agnostic ARM page table allocator.
*
* ARMv7 Short-descriptor format, supporting
* - Basic memory attributes
* - Simplified access permissions (AP[2:1] model)
* - Backwards-compatible TEX remap
* - Large pages/supersections (if indicated by the caller)
*
* Not supporting:
* - Legacy access permissions (AP[2:0] model)
*
* Almost certainly never supporting:
* - PXN
* - Domains
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* Copyright (C) 2014-2015 ARM Limited
* Copyright (c) 2014-2015 MediaTek Inc.
*/
#define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt
#include <linux/dma-mapping.h>
#include <linux/gfp.h>
#include <linux/iommu.h>
#include <linux/kernel.h>
#include <linux/kmemleak.h>
#include <linux/sizes.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <asm/barrier.h>
#include "io-pgtable.h"
/* Struct accessors */
#define io_pgtable_to_data(x) \
container_of((x), struct arm_v7s_io_pgtable, iop)
#define io_pgtable_ops_to_data(x) \
io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
/*
* We have 32 bits total; 12 bits resolved at level 1, 8 bits at level 2,
* and 12 bits in a page. With some carefully-chosen coefficients we can
* hide the ugly inconsistencies behind these macros and at least let the
* rest of the code pretend to be somewhat sane.
*/
#define ARM_V7S_ADDR_BITS 32
#define _ARM_V7S_LVL_BITS(lvl) (16 - (lvl) * 4)
#define ARM_V7S_LVL_SHIFT(lvl) (ARM_V7S_ADDR_BITS - (4 + 8 * (lvl)))
#define ARM_V7S_TABLE_SHIFT 10
#define ARM_V7S_PTES_PER_LVL(lvl) (1 << _ARM_V7S_LVL_BITS(lvl))
#define ARM_V7S_TABLE_SIZE(lvl) \
(ARM_V7S_PTES_PER_LVL(lvl) * sizeof(arm_v7s_iopte))
#define ARM_V7S_BLOCK_SIZE(lvl) (1UL << ARM_V7S_LVL_SHIFT(lvl))
#define ARM_V7S_LVL_MASK(lvl) ((u32)(~0U << ARM_V7S_LVL_SHIFT(lvl)))
#define ARM_V7S_TABLE_MASK ((u32)(~0U << ARM_V7S_TABLE_SHIFT))
#define _ARM_V7S_IDX_MASK(lvl) (ARM_V7S_PTES_PER_LVL(lvl) - 1)
#define ARM_V7S_LVL_IDX(addr, lvl) ({ \
int _l = lvl; \
((u32)(addr) >> ARM_V7S_LVL_SHIFT(_l)) & _ARM_V7S_IDX_MASK(_l); \
})
/*
* Large page/supersection entries are effectively a block of 16 page/section
* entries, along the lines of the LPAE contiguous hint, but all with the
* same output address. For want of a better common name we'll call them
* "contiguous" versions of their respective page/section entries here, but
* noting the distinction (WRT to TLB maintenance) that they represent *one*
* entry repeated 16 times, not 16 separate entries (as in the LPAE case).
*/
#define ARM_V7S_CONT_PAGES 16
/* PTE type bits: these are all mixed up with XN/PXN bits in most cases */
#define ARM_V7S_PTE_TYPE_TABLE 0x1
#define ARM_V7S_PTE_TYPE_PAGE 0x2
#define ARM_V7S_PTE_TYPE_CONT_PAGE 0x1
#define ARM_V7S_PTE_IS_VALID(pte) (((pte) & 0x3) != 0)
#define ARM_V7S_PTE_IS_TABLE(pte, lvl) (lvl == 1 && ((pte) & ARM_V7S_PTE_TYPE_TABLE))
/* Page table bits */
#define ARM_V7S_ATTR_XN(lvl) BIT(4 * (2 - (lvl)))
#define ARM_V7S_ATTR_B BIT(2)
#define ARM_V7S_ATTR_C BIT(3)
#define ARM_V7S_ATTR_NS_TABLE BIT(3)
#define ARM_V7S_ATTR_NS_SECTION BIT(19)
#define ARM_V7S_CONT_SECTION BIT(18)
#define ARM_V7S_CONT_PAGE_XN_SHIFT 15
/*
* The attribute bits are consistently ordered*, but occupy bits [17:10] of
* a level 1 PTE vs. bits [11:4] at level 2. Thus we define the individual
* fields relative to that 8-bit block, plus a total shift relative to the PTE.
*/
#define ARM_V7S_ATTR_SHIFT(lvl) (16 - (lvl) * 6)
#define ARM_V7S_ATTR_MASK 0xff
#define ARM_V7S_ATTR_AP0 BIT(0)
#define ARM_V7S_ATTR_AP1 BIT(1)
#define ARM_V7S_ATTR_AP2 BIT(5)
#define ARM_V7S_ATTR_S BIT(6)
#define ARM_V7S_ATTR_NG BIT(7)
#define ARM_V7S_TEX_SHIFT 2
#define ARM_V7S_TEX_MASK 0x7
#define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) << ARM_V7S_TEX_SHIFT)
/* *well, except for TEX on level 2 large pages, of course :( */
#define ARM_V7S_CONT_PAGE_TEX_SHIFT 6
#define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK << ARM_V7S_CONT_PAGE_TEX_SHIFT)
/* Simplified access permissions */
#define ARM_V7S_PTE_AF ARM_V7S_ATTR_AP0
#define ARM_V7S_PTE_AP_UNPRIV ARM_V7S_ATTR_AP1
#define ARM_V7S_PTE_AP_RDONLY ARM_V7S_ATTR_AP2
/* Register bits */
#define ARM_V7S_RGN_NC 0
#define ARM_V7S_RGN_WBWA 1
#define ARM_V7S_RGN_WT 2
#define ARM_V7S_RGN_WB 3
#define ARM_V7S_PRRR_TYPE_DEVICE 1
#define ARM_V7S_PRRR_TYPE_NORMAL 2
#define ARM_V7S_PRRR_TR(n, type) (((type) & 0x3) << ((n) * 2))
#define ARM_V7S_PRRR_DS0 BIT(16)
#define ARM_V7S_PRRR_DS1 BIT(17)
#define ARM_V7S_PRRR_NS0 BIT(18)
#define ARM_V7S_PRRR_NS1 BIT(19)
#define ARM_V7S_PRRR_NOS(n) BIT((n) + 24)
#define ARM_V7S_NMRR_IR(n, attr) (((attr) & 0x3) << ((n) * 2))
#define ARM_V7S_NMRR_OR(n, attr) (((attr) & 0x3) << ((n) * 2 + 16))
#define ARM_V7S_TTBR_S BIT(1)
#define ARM_V7S_TTBR_NOS BIT(5)
#define ARM_V7S_TTBR_ORGN_ATTR(attr) (((attr) & 0x3) << 3)
#define ARM_V7S_TTBR_IRGN_ATTR(attr) \
((((attr) & 0x1) << 6) | (((attr) & 0x2) >> 1))
#define ARM_V7S_TCR_PD1 BIT(5)
typedef u32 arm_v7s_iopte;
static bool selftest_running;
struct arm_v7s_io_pgtable {
struct io_pgtable iop;
arm_v7s_iopte *pgd;
struct kmem_cache *l2_tables;
};
static dma_addr_t __arm_v7s_dma_addr(void *pages)
{
return (dma_addr_t)virt_to_phys(pages);
}
static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl)
{
if (ARM_V7S_PTE_IS_TABLE(pte, lvl))
pte &= ARM_V7S_TABLE_MASK;
else
pte &= ARM_V7S_LVL_MASK(lvl);
return phys_to_virt(pte);
}
static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
struct arm_v7s_io_pgtable *data)
{
struct device *dev = data->iop.cfg.iommu_dev;
dma_addr_t dma;
size_t size = ARM_V7S_TABLE_SIZE(lvl);
void *table = NULL;
if (lvl == 1)
table = (void *)__get_dma_pages(__GFP_ZERO, get_order(size));
else if (lvl == 2)
table = kmem_cache_zalloc(data->l2_tables, gfp | GFP_DMA);
if (table && !selftest_running) {
dma = dma_map_single(dev, table, size, DMA_TO_DEVICE);
if (dma_mapping_error(dev, dma))
goto out_free;
/*
* We depend on the IOMMU being able to work with any physical
* address directly, so if the DMA layer suggests otherwise by
* translating or truncating them, that bodes very badly...
*/
if (dma != virt_to_phys(table))
goto out_unmap;
}
kmemleak_ignore(table);
return table;
out_unmap:
dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
out_free:
if (lvl == 1)
free_pages((unsigned long)table, get_order(size));
else
kmem_cache_free(data->l2_tables, table);
return NULL;
}
static void __arm_v7s_free_table(void *table, int lvl,
struct arm_v7s_io_pgtable *data)
{
struct device *dev = data->iop.cfg.iommu_dev;
size_t size = ARM_V7S_TABLE_SIZE(lvl);
if (!selftest_running)
dma_unmap_single(dev, __arm_v7s_dma_addr(table), size,
DMA_TO_DEVICE);
if (lvl == 1)
free_pages((unsigned long)table, get_order(size));
else
kmem_cache_free(data->l2_tables, table);
}
static void __arm_v7s_pte_sync(arm_v7s_iopte *ptep, int num_entries,
struct io_pgtable_cfg *cfg)
{
if (selftest_running)
return;
dma_sync_single_for_device(cfg->iommu_dev, __arm_v7s_dma_addr(ptep),
num_entries * sizeof(*ptep), DMA_TO_DEVICE);
}
static void __arm_v7s_set_pte(arm_v7s_iopte *ptep, arm_v7s_iopte pte,
int num_entries, struct io_pgtable_cfg *cfg)
{
int i;
for (i = 0; i < num_entries; i++)
ptep[i] = pte;
__arm_v7s_pte_sync(ptep, num_entries, cfg);
}
static arm_v7s_iopte arm_v7s_prot_to_pte(int prot, int lvl,
struct io_pgtable_cfg *cfg)
{
bool ap = !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS);
arm_v7s_iopte pte
|