path: root/drivers/infiniband/hw/nes/nes.h

/*
 * Copyright (c) 2006 - 2011 Intel Corporation.  All rights reserved.
 * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __NES_H
#define __NES_H

#include <linux/netdevice.h>
#include <linux/inetdevice.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <linux/crc32c.h>

#include <rdma/ib_smi.h>
#include <rdma/ib_verbs.h>
#include <rdma/ib_pack.h>
#include <rdma/rdma_cm.h>
#include <rdma/iw_cm.h>
#include <rdma/rdma_netlink.h>
#include <rdma/iw_portmap.h>

#define NES_SEND_FIRST_WRITE

#define QUEUE_DISCONNECTS

#define DRV_NAME    "iw_nes"
#define DRV_VERSION "1.5.0.1"
#define PFX         DRV_NAME ": "

/*
 * NetEffect PCI vendor id and NE010 PCI device id.
 */
#ifndef PCI_VENDOR_ID_NETEFFECT	/* not in pci.ids yet */
#define PCI_VENDOR_ID_NETEFFECT          0x1678
#define PCI_DEVICE_ID_NETEFFECT_NE020    0x0100
#define PCI_DEVICE_ID_NETEFFECT_NE020_KR 0x0110
#endif

#define NE020_REV   4
#define NE020_REV1  5

#define BAR_0       0
#define BAR_1       2

#define RX_BUF_SIZE             (1536 + 8)
#define NES_REG0_SIZE           (4 * 1024)
#define NES_TX_TIMEOUT          (6*HZ)
#define NES_FIRST_QPN           64
#define NES_SW_CONTEXT_ALIGN    1024

#define NES_MAX_MTU		9000

#define NES_NIC_MAX_NICS        16
#define NES_MAX_ARP_TABLE_SIZE  4096

#define NES_NIC_CEQ_SIZE        8
/* NICs will be on a separate CQ */
#define NES_CCEQ_SIZE ((nesadapter->max_cq / nesadapter->port_count) - 32)

#define NES_MAX_PORT_COUNT 4

#define MAX_DPC_ITERATIONS               128

#define NES_DRV_OPT_ENABLE_MPA_VER_0     0x00000001
#define NES_DRV_OPT_DISABLE_MPA_CRC      0x00000002
#define NES_DRV_OPT_DISABLE_FIRST_WRITE  0x00000004
#define NES_DRV_OPT_DISABLE_INTF         0x00000008
#define NES_DRV_OPT_ENABLE_MSI           0x00000010
#define NES_DRV_OPT_DUAL_LOGICAL_PORT    0x00000020
#define NES_DRV_OPT_SUPRESS_OPTION_BC    0x00000040
#define NES_DRV_OPT_NO_INLINE_DATA       0x00000080
#define NES_DRV_OPT_DISABLE_INT_MOD      0x00000100
#define NES_DRV_OPT_DISABLE_VIRT_WQ      0x00000200
#define NES_DRV_OPT_ENABLE_PAU           0x00000400

#define NES_AEQ_EVENT_TIMEOUT         2500
#define NES_DISCONNECT_EVENT_TIMEOUT  2000

/* debug levels */
/* must match userspace */
#define NES_DBG_HW          0x00000001
#define NES_DBG_INIT        0x00000002
#define NES_DBG_ISR         0x00000004
#define NES_DBG_PHY         0x00000008
#define NES_DBG_NETDEV      0x00000010
#define NES_DBG_CM          0x00000020
#define NES_DBG_CM1         0x00000040
#define NES_DBG_NIC_RX      0x00000080
#define NES_DBG_NIC_TX      0x00000100
#define NES_DBG_CQP         0x00000200
#define NES_DBG_MMAP        0x00000400
#define NES_DBG_MR          0x00000800
#define NES_DBG_PD          0x00001000
#define NES_DBG_CQ          0x00002000
#define NES_DBG_QP          0x00004000
#define NES_DBG_MOD_QP      0x00008000
#define NES_DBG_AEQ         0x00010000
#define NES_DBG_IW_RX       0x00020000
#define NES_DBG_IW_TX       0x00040000
#define NES_DBG_SHUTDOWN    0x00080000
#define NES_DBG_PAU         0x00100000
#define NES_DBG_NLMSG       0x00200000
#define NES_DBG_RSVD1       0x10000000
#define NES_DBG_RSVD2       0x20000000
#define NES_DBG_RSVD3       0x40000000
#define NES_DBG_RSVD4       0x80000000
#define NES_DBG_ALL         0xffffffff

#ifdef CONFIG_INFINIBAND_NES_DEBUG
#define nes_debug(level, fmt, args...) \
do { \
	if (level & nes_debug_level) \
		printk(KERN_ERR PFX "%s[%u]: " fmt, __func__, __LINE__, ##args); \
} while (0)

#define NES_EVENT_TIMEOUT   1200000
#else
#define nes_debug(level, fmt, args...) no_printk(fmt, ##args)

#define NES_EVENT_TIMEOUT   100000
#endif

#include "nes_hw.h"
#include "nes_verbs.h"
#include "nes_context.h"
#include <rdma/nes-abi.h>
#include "nes_cm.h"
#include "nes_mgt.h"

extern int interrupt_mod_interval;
extern int nes_if_count;
extern int mpa_version;
extern int disable_mpa_crc;
extern unsigned int nes_drv_opt;
extern unsigned int nes_debug_level;
extern unsigned int wqm_quanta;
extern struct list_head nes_adapter_list;

extern atomic_t cm_connects;
extern atomic_t cm_accepts;
extern atomic_t cm_disconnects;
extern atomic_t cm_closes;
extern atomic_t cm_connecteds;
extern atomic_t cm_connect_reqs;
extern atomic_t cm_rejects;
extern atomic_t mod_qp_timouts;
extern atomic_t qps_created;
extern atomic_t qps_destroyed;
extern atomic_t sw_qps_destroyed;
extern u32 mh_detected;
extern u32 mh_pauses_sent;
extern u32 cm_packets_sent;
extern u32 cm_packets_bounced;
extern u32 cm_packets_created;
extern u32 cm_packets_received;
extern u32 cm_packets_dropped;
extern u32 cm_packets_retrans;
extern atomic_t cm_listens_created;
extern atomic_t cm_listens_destroyed;
extern u32 cm_backlog_drops;
extern atomic_t cm_loopbacks;
extern atomic_t cm_nodes_created;
extern atomic_t cm_nodes_destroyed;
extern atomic_t cm_accel_dropped_pkts;
extern atomic_t cm_resets_recvd;
extern atomic_t pau_qps_created;
extern atomic_t pau_qps_destroyed;

extern u32 int_mod_timer_init;
extern u32 int_mod_cq_depth_256;
extern u32 int_mod_cq_depth_128;
extern u32 int_mod_cq_depth_32;
extern u32 int_mod_cq_depth_24;
extern u32 int_mod_cq_depth_16;
extern u32 int_mod_cq_depth_4;
extern u32 int_mod_cq_depth_1;

struct nes_device {
	struct nes_adapter	   *nesadapter;
	void __iomem           *regs;
	void __iomem           *index_reg;
	struct pci_dev         *pcidev;
	struct net_device      *netdev[NES_NIC_MAX_NICS];
	u64                    link_status_interrupts;
	struct tasklet_struct  dpc_tasklet;
	spinlock_t             indexed_regs_lock;
	unsigned long          csr_start;
	unsigned long          doorbell_region;
	unsigned long          doorbell_start;
	unsigned long          mac_tx_errors;
	unsigned long          mac_pause_frames_sent;
	unsigned long          mac_pause_frames_received;
	unsigned long          mac_rx_errors;
	unsigned long          mac_rx_crc_errors;
	unsigned long          mac_rx_symbol_err_frames;
	unsigned long          mac_rx_jabber_frames;
	unsigned long          mac_rx_oversized_frames;
	unsigned long          mac_rx_short_frames;
	unsigned long          port_rx_discards;
	unsigned long          port_tx_discards;
	unsigned int           mac_index;
	unsigned int           nes_stack_start;

	/* Control Structures */
	void                   *cqp_vbase;
	dma_addr_t             cqp_pbase;
	u32                    cqp_mem_size;
	u8                     ceq_index;
	u8                     nic_ceq_index;
	struct nes_hw_cqp      cqp;
	struct nes_hw_cq       ccq;
	struct list_head       cqp_avail_reqs;
	struct list_head       cqp_pending_reqs;
	struct nes_cqp_request *nes_cqp_requests;

	u32                    int_req;
	u32                    int_stat;
	u32                    timer_int_req;
	u32                    timer_only_int_count;
	u32                    intf_int_req;
	u32                    last_mac_tx_pauses;
	u32                    last_used_chunks_tx;
	struct list_head       list;

	u16                    base_doorbell_index;
	u16                    currcq_count;
	u16                    deepcq_count;
	u8                     iw_status;
	u8                     msi_enabled;
	u8                     netdev_count;
	u8                     napi_isr_ran;
	u8                     disable_rx_flow_control;
	u8                     disable_tx_flow_control;

	struct delayed_work    work;
	u8                     link_recheck;
};

/* Receive skb private area - must fit in skb->cb area */
struct nes_rskb_cb {
	u64                    busaddr;
	u32                    maplen;
	u32                    seqnum;
	u8                     *data_start;
	struct nes_qp          *nesqp;
};

static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad)
{
	u32 crc_value;
	crc_value = crc32c(~0, (void *)nes_quad, sizeof (struct nes_v4_quad));

	/*
	 * With commit ef19454b ("[LIB] crc32c: Keep intermediate crc
	 * state in cpu order"), behavior of crc32c changes on
	 * big-endian platforms.  Our algorithm expects the previous
	 * behavior; otherwise we have RDMA connection establishment
	 * issue on big-endian.
	 */
	return cpu_to_le32(crc_value);
}

static inline void
set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value)
{
	wqe_words[index]     = cpu_to_le32((u32) value);
	wqe_words[index + 1] = cpu_to_le32(upper_32_bits(value));
}

static inline void
set_wqe_32bit_value(__le32 *wqe_words, u32 index, u32 value)
{
	wqe_words[index] = cpu_to_le32(value);
}

static inline void
nes_fill_init_cqp_wqe(struct nes_hw_cqp_wqe *cqp_wqe, struct nes_device *nesdev)
{
	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX]       = 0;
	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX]      = 0;
	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX]   = 0;
	cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX]  = 0;
	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX] = 0;
	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_LEN_IDX]       = 0;
	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_LEN_LOW_IDX]       = 0;
	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_LOW_IDX]        = 0;
	cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_HIGH_IDX]       = 0;
}