#ifndef DEF_CHIP_REG
#define DEF_CHIP_REG
/*
* Copyright(c) 2015, 2016 Intel Corporation.
*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* GPL LICENSE SUMMARY
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* BSD LICENSE
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#define CORE 0x000000000000
#define CCE (CORE + 0x000000000000)
#define ASIC (CORE + 0x000000400000)
#define MISC (CORE + 0x000000500000)
#define DC_TOP_CSRS (CORE + 0x000000600000)
#define CHIP_DEBUG (CORE + 0x000000700000)
#define RXE (CORE + 0x000001000000)
#define TXE (CORE + 0x000001800000)
#define DCC_CSRS (DC_TOP_CSRS + 0x000000000000)
#define DC_LCB_CSRS (DC_TOP_CSRS + 0x000000001000)
#define DC_8051_CSRS (DC_TOP_CSRS + 0x000000002000)
#define PCIE 0
#define ASIC_NUM_SCRATCH 4
#define CCE_ERR_INT_CNT 0
#define CCE_MISC_INT_CNT 2
#define CCE_NUM_32_BIT_COUNTERS 3
#define CCE_NUM_32_BIT_INT_COUNTERS 6
#define CCE_NUM_INT_CSRS 12
#define CCE_NUM_INT_MAP_CSRS 96
#define CCE_NUM_MSIX_PBAS 4
#define CCE_NUM_MSIX_VECTORS 256
#define CCE_NUM_SCRATCH 4
#define CCE_PCIE_POSTED_CRDT_STALL_CNT 2
#define CCE_PCIE_TRGT_STALL_CNT 0
#define CCE_PIO_WR_STALL_CNT 1
#define CCE_RCV_AVAIL_INT_CNT 3
#define CCE_RCV_URGENT_INT_CNT 4
#define CCE_SDMA_INT_CNT 1
#define CCE_SEND_CREDIT_INT_CNT 5
#define DCC_CFG_LED_CNTRL (DCC_CSRS + 0x000000000040)
#define DCC_CFG_LED_CNTRL_LED_CNTRL_SMASK 0x10ull
#define DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SHIFT 0
#define DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SMASK 0xFull
#define DCC_CFG_PORT_CONFIG (DCC_CSRS + 0x000000000008)
#define DCC_CFG_PORT_CONFIG1 (DCC_CSRS + 0x000000000010)
#define DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK 0xFFFFull
#define DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT 16
#define DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK 0xFFFF0000ull
#define DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK 0xFFFFull
#define DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT 0
#define DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK 0xFFFFull
#define DCC_CFG_PORT_CONFIG_LINK_STATE_MASK 0x7ull
#define DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT 48
#define DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK 0x7000000000000ull
#define DCC_CFG_PORT_CONFIG_MTU_CAP_MASK 0x7ull
#define DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT 32
#define DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK 0x700000000ull
#define DCC_CFG_RESET (DCC_CSRS + 0x000000000000)
#define DCC_CFG_RESET_RESET_LCB BIT_ULL(0)
#define DCC_CFG_RESET_RESET_TX_FPE BIT_ULL(1)
#define DCC_CFG_RESET_RESET_RX_FPE BIT_ULL(2)
#define DCC_CFG_RESET_RESET_8051 BIT_ULL(3)
#define DCC_CFG_RESET_ENABLE_CCLK_BCC BIT_ULL(4)
#define DCC_CFG_SC_VL_TABLE_15_0 (DCC_CSRS + 0x000000000028)
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY0_SHIFT 0
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY10_SHIFT 40
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY11_SHIFT 44
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY12_SHIFT 48
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY13_SHIFT 52
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY14_SHIFT 56
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY15_SHIFT 60
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY1_SHIFT 4
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY2_SHIFT 8
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY3_SHIFT 12
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY4_SHIFT 16
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY5_SHIFT 20
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY6_SHIFT 24
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY7_SHIFT 28
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY8_SHIFT 32
#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY9_SHIFT 36
#define DCC_CFG_SC_VL_TABLE_31_16 (DCC_CSRS + 0x000000000030)
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY16_SHIFT 0
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY17_SHIFT 4
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY18_SHIFT 8
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY19_SHIFT 12
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY20_SHIFT 16
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY21_SHIFT 20
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY22_SHIFT 24
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY23_SHIFT 28
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY24_SHIFT 32
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY25_SHIFT 36
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY26_SHIFT 40
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY27_SHIFT 44
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY28_SHIFT 48
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY29_SHIFT 52
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY30_SHIFT 56
#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY31_SHIFT 60
#define DCC_ERR_DROPPED_PKT_CNT (DCC_CSRS + 0x000000000120)
#define DCC_ERR_FLG (DCC_CSRS + 0x000000000050)
#define DCC_ERR_FLG_BAD_CRDT_ACK_ERR_SMASK 0x4000ull
#define DCC_ERR_FLG_BAD_CTRL_DIST_ERR_SMASK 0x200000ull
#define DCC_ERR_FLG_BAD_CTRL_FLIT_ERR_SMASK 0x10000ull
#define DCC_ERR_FLG_BAD_DLID_TARGET_ERR_SMASK 0x200ull
#define DCC_ERR_FLG_BAD_HEAD_DIST_ERR_SMASK 0x800000ull
#define DCC_ERR_FLG_BAD_L2_ERR_SMASK 0x2ull
#define DCC_ERR_FLG_BAD_LVE