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/*
* max30102.c - Support for MAX30102 heart rate and pulse oximeter sensor
*
* Copyright (C) 2017 Matt Ranostay <matt@ranostay.consulting>
*
* Support for MAX30105 optical particle sensor
* Copyright (C) 2017 Peter Meerwald-Stadler <pmeerw@pmeerw.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* 7-bit I2C chip address: 0x57
* TODO: proximity power saving feature
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/kfifo_buf.h>
#define MAX30102_REGMAP_NAME "max30102_regmap"
#define MAX30102_DRV_NAME "max30102"
#define MAX30102_PART_NUMBER 0x15
enum max30102_chip_id {
max30102,
max30105,
};
enum max3012_led_idx {
MAX30102_LED_RED,
MAX30102_LED_IR,
MAX30105_LED_GREEN,
};
#define MAX30102_REG_INT_STATUS 0x00
#define MAX30102_REG_INT_STATUS_PWR_RDY BIT(0)
#define MAX30102_REG_INT_STATUS_PROX_INT BIT(4)
#define MAX30102_REG_INT_STATUS_ALC_OVF BIT(5)
#define MAX30102_REG_INT_STATUS_PPG_RDY BIT(6)
#define MAX30102_REG_INT_STATUS_FIFO_RDY BIT(7)
#define MAX30102_REG_INT_ENABLE 0x02
#define MAX30102_REG_INT_ENABLE_PROX_INT_EN BIT(4)
#define MAX30102_REG_INT_ENABLE_ALC_OVF_EN BIT(5)
#define MAX30102_REG_INT_ENABLE_PPG_EN BIT(6)
#define MAX30102_REG_INT_ENABLE_FIFO_EN BIT(7)
#define MAX30102_REG_INT_ENABLE_MASK 0xf0
#define MAX30102_REG_INT_ENABLE_MASK_SHIFT 4
#define MAX30102_REG_FIFO_WR_PTR 0x04
#define MAX30102_REG_FIFO_OVR_CTR 0x05
#define MAX30102_REG_FIFO_RD_PTR 0x06
#define MAX30102_REG_FIFO_DATA 0x07
#define MAX30102_REG_FIFO_DATA_BYTES 3
#define MAX30102_REG_FIFO_CONFIG 0x08
#define MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES BIT(1)
#define MAX30102_REG_FIFO_CONFIG_AVG_SHIFT 5
#define MAX30102_REG_FIFO_CONFIG_AFULL BIT(0)
#define MAX30102_REG_MODE_CONFIG 0x09
#define MAX30102_REG_MODE_CONFIG_MODE_NONE 0x00
#define MAX30102_REG_MODE_CONFIG_MODE_HR 0x02 /* red LED */
#define MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2 0x03 /* red + IR LED */
#define MAX30102_REG_MODE_CONFIG_MODE_MULTI 0x07 /* multi-LED mode */
#define MAX30102_REG_MODE_CONFIG_MODE_MASK GENMASK(2, 0)
#define MAX30102_REG_MODE_CONFIG_PWR BIT(7)
#define MAX30102_REG_MODE_CONTROL_SLOT21 0x11 /* multi-LED control */
#define MAX30102_REG_MODE_CONTROL_SLOT43 0x12
#define MAX30102_REG_MODE_CONTROL_SLOT_MASK (GENMASK(6, 4) | GENMASK(2, 0))
#define MAX30102_REG_MODE_CONTROL_SLOT_SHIFT 4
#define MAX30102_REG_SPO2_CONFIG 0x0a
#define MAX30102_REG_SPO2_CONFIG_PULSE_411_US 0x03
#define MAX30102_REG_SPO2_CONFIG_SR_400HZ 0x03
#define MAX30102_REG_SPO2_CONFIG_SR_MASK 0x07
#define MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT 2
#define MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS BIT(0)
#define MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT 5
#define MAX30102_REG_RED_LED_CONFIG 0x0c
#define MAX30102_REG_IR_LED_CONFIG 0x0d
#define MAX30105_REG_GREEN_LED_CONFIG 0x0e
#define MAX30102_REG_TEMP_CONFIG 0x21
#define MAX30102_REG_TEMP_CONFIG_TEMP_EN BIT(0)
#define MAX30102_REG_TEMP_INTEGER 0x1f
#define MAX30102_REG_TEMP_FRACTION 0x20
#define MAX30102_REG_REV_ID 0xfe
#define MAX30102_REG_PART_ID 0xff
struct max30102_data {
struct i2c_client *client;
struct iio_dev *indio_dev;
struct mutex lock;
struct regmap *regmap;
enum max30102_chip_id chip_id;
u8 buffer[12];
__be32 processed_buffer[3]; /* 3 x 18-bit (padded to 32-bits) */
};
static const struct regmap_config max30102_regmap_config = {
.name = MAX30102_REGMAP_NAME,
.reg_bits = 8,
.val_bits = 8,
};
static const unsigned long max30102_scan_masks[] = {
BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
0
};
static const unsigned long max30105_scan_masks[] = {
BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
BIT(MAX30105_LED_GREEN),
0
};
#define MAX30102_INTENSITY_CHANNEL(_si, _mod) { \
.type = IIO_INTENSITY, \
.channel2 = _mod, \
.modified = 1, \
.scan_index = _si, \
.scan_type = { \
.sign = 'u', \
.shift = 8, \
.realbits = 18, \
.storagebits = 32, \
.endianness = IIO_BE, \
}, \
}
static const struct iio_chan_spec max30102_channels[] = {
MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
{
.type = IIO_TEMP,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = -1,
},
};
static const struct iio_chan_spec max30105_channels[] = {
MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
MAX30102_INTENSITY_CHANNEL(MAX30105_LED_GREEN, IIO_MOD_LIGHT_GREEN),
{
.type = IIO_TEMP,
.info_mask_separate =
BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
.scan_index = -1,
},
};
static int max30102_set_power(struct max30102_data *data, bool en)
{
return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
MAX30102_REG_MODE_CONFIG_PWR,
en ? 0 : MAX30102_REG_MODE_CONFIG_PWR);
}
static int max30102_set_powermode(struct max30102_data *data, u8 mode, bool en)
{
u8 reg = mode;
if (!en)
reg |= MAX30102_REG_MODE_CONFIG_PWR;
return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
MAX30102_REG_MODE_CONFIG_PWR |
MAX30102_REG_MODE_CONFIG_MODE_MASK, reg);
}
#define MAX30102_MODE_CONTROL_LED_SLOTS(slot2, slot1) \
((slot2 << MAX30102_REG_MODE_CONTROL_SLOT_SHIFT) | slot1)
static int max30102_buffer_postenable(struct iio_dev *indio_dev)
{
struct max30102_data *data = iio_priv(indio_dev);
int ret;
u8 reg;
switch (*indio_dev->active_scan_mask) {
case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR):
reg = MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2;
break;
case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
BIT(MAX30105_LED_GREEN):
ret = regmap_update_bits(data->regmap,
MAX30102_REG_MODE_CONTROL_SLOT21,
MAX30102_REG_MODE_CONTROL_SLOT_MASK,
MAX30102_MODE_CONTROL_LED_SLOTS(2, 1));
if (ret)
return ret;
ret = regmap_update_bits(data->regmap,
MAX30102_REG_MODE_CONTROL_SLOT43,
MAX30102_REG_MODE_CONTROL_SLOT_MASK,
MAX30102_MODE_CONTROL_LED_SLOTS(0, 3));
if (ret)
return ret;
reg = MAX30102_REG_MODE_CONFIG_MODE_MULTI;
break;
default:
return -EINVAL;
}
return max30102_set_powermode(data, reg, true);
}
static int max30102_buffer_predisable(struct iio_dev *indio_dev)
{
struct max30102_data *data = iio_priv(indio_dev);
return max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
false);
}
static const struct iio_buffer_setup_ops max30102_buffer_setup_ops = {
.postenable = max30102_buffer_postenable,
.predisable = max30102_buffer_predisable,
};
static inline int max30102_fifo_count(struct max30102_data *data)
{
unsigned int val;
int ret;
ret = regmap_read(data->regmap, MAX30102_REG_INT_STATUS, &val);
if (ret)
return ret;
/* FIFO has one sample slot left */
if (val & MAX30102_REG_INT_STATUS_FIFO_RDY)
return 1;
return 0;
}
#define MAX30102_COPY_DATA(i) \
memcpy(&data->processed_buffer[(i)], \
&buffer[(i) * MAX30102_REG_FIFO_DATA_BYTES], \
MAX30102_REG_FIFO_DATA_BYTES)
static int max30102_read_measurement(struct max30102_data *data,
unsigned int measurements)
{
int ret;
u8 *buffer = (u8 *) &data->buffer;
ret = i2c_smbus_read_i2c_block_data(data->client,
MAX30102_REG_FIFO_DATA,
measurements *
MAX30102_REG_FIFO_DATA_BYTES,
buffer);
switch (measurements) {
case 3:
MAX30102_COPY_DATA(2);
/* fall through */
case 2:
MAX30102_COPY_DATA(1);
/* fall through */
case 1:
MAX30102_COPY_DATA(0);
break;
default:
return -EINVAL;
}
return (ret == measurements * MAX30102_REG_FIFO_DATA_BYTES) ?
0 : -EINVAL;
}
static irqreturn_t max30102_interrupt_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
struct
|