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|
/*
* AD9523 SPI Low Jitter Clock Generator
*
* Copyright 2012 Analog Devices Inc.
*
* Licensed under the GPL-2.
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/frequency/ad9523.h>
#define AD9523_READ (1 << 15)
#define AD9523_WRITE (0 << 15)
#define AD9523_CNT(x) (((x) - 1) << 13)
#define AD9523_ADDR(x) ((x) & 0xFFF)
#define AD9523_R1B (1 << 16)
#define AD9523_R2B (2 << 16)
#define AD9523_R3B (3 << 16)
#define AD9523_TRANSF_LEN(x) ((x) >> 16)
#define AD9523_SERIAL_PORT_CONFIG (AD9523_R1B | 0x0)
#define AD9523_VERSION_REGISTER (AD9523_R1B | 0x2)
#define AD9523_PART_REGISTER (AD9523_R1B | 0x3)
#define AD9523_READBACK_CTRL (AD9523_R1B | 0x4)
#define AD9523_EEPROM_CUSTOMER_VERSION_ID (AD9523_R2B | 0x6)
#define AD9523_PLL1_REF_A_DIVIDER (AD9523_R2B | 0x11)
#define AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B | 0x13)
#define AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B | 0x14)
#define AD9523_PLL1_FEEDBACK_DIVIDER (AD9523_R2B | 0x17)
#define AD9523_PLL1_CHARGE_PUMP_CTRL (AD9523_R2B | 0x19)
#define AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B | 0x1A)
#define AD9523_PLL1_REF_CTRL (AD9523_R1B | 0x1B)
#define AD9523_PLL1_MISC_CTRL (AD9523_R1B | 0x1C)
#define AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B | 0x1D)
#define AD9523_PLL2_CHARGE_PUMP (AD9523_R1B | 0xF0)
#define AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B | 0xF1)
#define AD9523_PLL2_CTRL (AD9523_R1B | 0xF2)
#define AD9523_PLL2_VCO_CTRL (AD9523_R1B | 0xF3)
#define AD9523_PLL2_VCO_DIVIDER (AD9523_R1B | 0xF4)
#define AD9523_PLL2_LOOP_FILTER_CTRL (AD9523_R2B | 0xF6)
#define AD9523_PLL2_R2_DIVIDER (AD9523_R1B | 0xF7)
#define AD9523_CHANNEL_CLOCK_DIST(ch) (AD9523_R3B | (0x192 + 3 * ch))
#define AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B | 0x1BA)
#define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB)
#define AD9523_READBACK_0 (AD9523_R1B | 0x22C)
#define AD9523_READBACK_1 (AD9523_R1B | 0x22D)
#define AD9523_STATUS_SIGNALS (AD9523_R3B | 0x232)
#define AD9523_POWER_DOWN_CTRL (AD9523_R1B | 0x233)
#define AD9523_IO_UPDATE (AD9523_R1B | 0x234)
#define AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B | 0xB00)
#define AD9523_EEPROM_ERROR_READBACK (AD9523_R1B | 0xB01)
#define AD9523_EEPROM_CTRL1 (AD9523_R1B | 0xB02)
#define AD9523_EEPROM_CTRL2 (AD9523_R1B | 0xB03)
/* AD9523_SERIAL_PORT_CONFIG */
#define AD9523_SER_CONF_SDO_ACTIVE (1 << 7)
#define AD9523_SER_CONF_SOFT_RESET (1 << 5)
/* AD9523_READBACK_CTRL */
#define AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0)
/* AD9523_PLL1_CHARGE_PUMP_CTRL */
#define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x) (((x) / 500) & 0x7F)
#define AD9523_PLL1_CHARGE_PUMP_TRISTATE (1 << 7)
#define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)
#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8)
#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8)
#define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8)
#define AD9523_PLL1_BACKLASH_PW_MIN (0 << 10)
#define AD9523_PLL1_BACKLASH_PW_LOW (1 << 10)
#define AD9523_PLL1_BACKLASH_PW_HIGH (2 << 10)
#define AD9523_PLL1_BACKLASH_PW_MAX (3 << 10)
/* AD9523_PLL1_INPUT_RECEIVERS_CTRL */
#define AD9523_PLL1_REF_TEST_RCV_EN (1 << 7)
#define AD9523_PLL1_REFB_DIFF_RCV_EN (1 << 6)
#define AD9523_PLL1_REFA_DIFF_RCV_EN (1 << 5)
#define AD9523_PLL1_REFB_RCV_EN (1 << 4)
#define AD9523_PLL1_REFA_RCV_EN (1 << 3)
#define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2)
#define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1)
#define AD9523_PLL1_OSC_IN_DIFF_EN (1 << 0)
/* AD9523_PLL1_REF_CTRL */
#define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN (1 << 7)
#define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN (1 << 6)
#define AD9523_PLL1_ZERO_DELAY_MODE_INT (1 << 5)
#define AD9523_PLL1_ZERO_DELAY_MODE_EXT (0 << 5)
#define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN (1 << 4)
#define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN (1 << 3)
#define AD9523_PLL1_ZD_IN_DIFF_EN (1 << 2)
#define AD9523_PLL1_REFB_CMOS_NEG_INP_EN (1 << 1)
#define AD9523_PLL1_REFA_CMOS_NEG_INP_EN (1 << 0)
/* AD9523_PLL1_MISC_CTRL */
#define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN (1 << 7)
#define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 6)
#define AD9523_PLL1_REF_MODE(x) ((x) << 2)
#define AD9523_PLL1_BYPASS_REFB_DIV (1 << 1)
#define AD9523_PLL1_BYPASS_REFA_DIV (1 << 0)
/* AD9523_PLL1_LOOP_FILTER_CTRL */
#define AD9523_PLL1_LOOP_FILTER_RZERO(x) ((x) & 0xF)
/* AD9523_PLL2_CHARGE_PUMP */
#define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x) ((x) / 3500)
/* AD9523_PLL2_FEEDBACK_DIVIDER_AB */
#define AD9523_PLL2_FB_NDIV_A_CNT(x) (((x) & 0x3) << 6)
#define AD9523_PLL2_FB_NDIV_B_CNT(x) (((x) & 0x3F) << 0)
#define AD9523_PLL2_FB_NDIV(a, b) (4 * (b) + (a))
/* AD9523_PLL2_CTRL */
#define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)
#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0)
#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0)
#define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0)
#define AD9523_PLL2_BACKLASH_PW_MIN (0 << 2)
#define AD9523_PLL2_BACKLASH_PW_LOW (1 << 2)
#define AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2)
#define AD9523_PLL2_BACKLASH_PW_MAX (3 << 1)
#define AD9523_PLL2_BACKLASH_CTRL_EN (1 << 4)
#define AD9523_PLL2_FREQ_DOUBLER_EN (1 << 5)
#define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)
/* AD9523_PLL2_VCO_CTRL */
#define AD9523_PLL2_VCO_CALIBRATE (1 << 1)
#define AD9523_PLL2_FORCE_VCO_MIDSCALE (1 << 2)
#define AD9523_PLL2_FORCE_REFERENCE_VALID (1 << 3)
#define AD9523_PLL2_FORCE_RELEASE_SYNC (1 << 4)
/* AD9523_PLL2_VCO_DIVIDER */
#define AD9523_PLL2_VCO_DIV_M1(x) ((((x) - 3) & 0x3) << 0)
#define AD9523_PLL2_VCO_DIV_M2(x) ((((x) - 3) & 0x3) << 4)
#define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 2)
#define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN (1 << 6)
/* AD9523_PLL2_LOOP_FILTER_CTRL */
#define AD9523_PLL2_LOOP_FILTER_CPOLE1(x) (((x) & 0x7) << 0)
#define AD9523_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3)
#define AD9523_PLL2_LOOP_FILTER_RPOLE2(x) (((x) & 0x7) << 6)
#define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)
/* AD9523_PLL2_R2_DIVIDER */
#define AD9523_PLL2_R2_DIVIDER_VAL(x) (((x) & 0x1F) << 0)
/* AD9523_CHANNEL_CLOCK_DIST */
#define AD9523_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 18)
#define AD9523_CLK_DIST_DIV_PHASE_REV(x) ((ret >> 18) & 0x3F)
#define AD9523_CLK_DIST_DIV(x) ((((x) - 1) & 0x3FF) << 8)
#define AD9523_CLK_DIST_DIV_REV(x) (((ret >> 8) & 0x3FF) + 1)
#define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7)
#define AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6)
#define AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5)
#define AD9523_CLK_DIST_LOW_PWR_MODE_EN (1 << 4)
#define AD9523_CLK_DIST_DRIVER_MODE(x) (((x) & 0xF) << 0)
/* AD9523_PLL1_OUTPUT_CTRL */
#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2 (1 << 7)
#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6)
#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 (1 << 5)
#define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK (1 << 4)
#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1 (0 << 0)
#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2 (1 << 0)
#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4 (2 << 0)
#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8 (4 << 0)
#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16 (8 << 0)
/* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */
#define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7)
#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6)
#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5)
#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4)
#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3 (1 << 3)
#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2 (1 << 2)
#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1 (1 << 1)
#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 (1 << 0)
/* AD9523_READBACK_0 */
#define AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7)
#define AD9523_READBACK_0_STAT_PLL2_FB_CLK (1 << 6)
#define AD9523_READBACK_0_STAT_VCXO (1 << 5)
#define AD9523_READBACK_0_STAT_REF_TEST (1 << 4)
#define AD9523_READBACK_0_STAT_REFB (1 << 3)
#define AD9523_READBACK_0_STAT_REFA (1 << 2)
#define AD9523_READBACK_0_STAT_PLL2_LD (1 << 1)
#define AD9523_READBACK_0_STAT_PLL1_LD (1 << 0)
/* AD9523_READBACK_1 */
#define AD9523_READBACK_1_HOLDOVER_ACTIVE (1 << 3)
#define AD9523_READBACK_1_AUTOMODE_SEL_REFB (1 << 2)
#define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS (1 << 0)
/* AD9523_STATUS_SIGNALS */
#define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL (1 << 16)
#define AD9523_STATUS_MONITOR_01_PLL12_LOCKED (0x302)
/* AD9523_POWER_DOWN_CTRL */
#define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN (1 << 2)
#define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN (1 << 1)
#define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN (1 << 0)
/* AD9523_IO_UPDATE */
#define AD9523_IO_UPDATE_EN (1 << 0)
/* AD9523_EEPROM_DATA_XFER_STATUS */
#define AD9523_EEPROM_DATA_XFER_IN_PROGRESS (1 << 0)
/* AD9523_EEPROM_ERROR_READBACK */
#define AD9523_EEPROM_ERROR_READBACK_FAIL (1 << 0)
/* AD9523_EEPROM_CTRL1 */
#define AD9523_EEPROM_CTRL1_SOFT_EEPROM (1 << 1)
#define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS (1 << 0)
/* AD9523_EEPROM_CTRL2 */
#define AD9523_EEPROM_CTRL2_REG2EEPROM (1 << 0)
#define AD9523_NUM_CHAN 14
#define AD9523_NUM_CHAN_ALT_CLK_SRC 10
/* Helpers to avoid excess line breaks */
#define AD_IFE(_pde, _a, _b) ((pdata->_pde) ? _a : _b)
#define AD_IF(_pde, _a) AD_IFE(_pde, _a, 0)
enum {
AD9523_STAT_PLL1_LD,
AD9523_STAT_PLL2_LD,
AD9523_STAT_REFA,
AD9523_STAT_REFB,
AD9523_STAT_REF_TEST,
AD9523_STAT_VCXO,
AD9523_STAT_PLL2_FB_CLK,
AD9523_STAT_PLL2_REF_CLK,
AD9523_SYNC,
AD9523_EEPROM,
};
enum {
AD9523_VCO1,
AD9523_VCO2,
AD9523_VCXO,
AD9523_NUM_CLK_SRC,
};
struct ad9523_state {
struct spi_device *spi;
struct regulator *reg;
struct ad9523_platform_data *pdata;
struct iio_chan_spec ad9523_channels[AD9523_NUM_CHAN];
struct gpio_desc *pwrdown_gpio;
struct gpio_desc *reset_gpio;
struct gpio_desc *sync_gpio;
unsigned long vcxo_freq;
unsigned long vco_freq;
unsigned long vco_out_freq[AD9523_NUM_CLK_SRC];
unsigned <
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