1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Analog devices AD5764, AD5764R, AD5744, AD5744R quad-channel
* Digital to Analog Converters driver
*
* Copyright 2011 Analog Devices Inc.
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#define AD5764_REG_SF_NOP 0x0
#define AD5764_REG_SF_CONFIG 0x1
#define AD5764_REG_SF_CLEAR 0x4
#define AD5764_REG_SF_LOAD 0x5
#define AD5764_REG_DATA(x) ((2 << 3) | (x))
#define AD5764_REG_COARSE_GAIN(x) ((3 << 3) | (x))
#define AD5764_REG_FINE_GAIN(x) ((4 << 3) | (x))
#define AD5764_REG_OFFSET(x) ((5 << 3) | (x))
#define AD5764_NUM_CHANNELS 4
/**
* struct ad5764_chip_info - chip specific information
* @int_vref: Value of the internal reference voltage in uV - 0 if external
* reference voltage is used
* @channels: channel specification
*/
struct ad5764_chip_info {
unsigned long int_vref;
const struct iio_chan_spec *channels;
};
/**
* struct ad5764_state - driver instance specific data
* @spi: spi_device
* @chip_info: chip info
* @vref_reg: vref supply regulators
* @lock: lock to protect the data buffer during SPI ops
* @data: spi transfer buffers
*/
struct ad5764_state {
struct spi_device *spi;
const struct ad5764_chip_info *chip_info;
struct regulator_bulk_data vref_reg[2];
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) requires the
* transfer buffers to live in their own cache lines.
*/
union {
__be32 d32;
u8 d8[4];
} data[2] ____cacheline_aligned;
};
enum ad5764_type {
ID_AD5744,
ID_AD5744R,
ID_AD5764,
ID_AD5764R,
};
#define AD5764_CHANNEL(_chan, _bits) { \
.type = IIO_VOLTAGE, \
.indexed = 1, \
.output = 1, \
.channel = (_chan), \
.address = (_chan), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_CALIBSCALE) | \
BIT(IIO_CHAN_INFO_CALIBBIAS), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET), \
.scan_type = { \
.sign = 'u', \
.realbits = (_bits), \
.storagebits = 16, \
.shift = 16 - (_bits), \
}, \
}
#define DECLARE_AD5764_CHANNELS(_name, _bits) \
const struct iio_chan_spec _name##_channels[] = { \
AD5764_CHANNEL(0, (_bits)), \
AD5764_CHANNEL(1, (_bits)), \
AD5764_CHANNEL(2, (_bits)), \
AD5764_CHANNEL(3, (_bits)), \
};
static DECLARE_AD5764_CHANNELS(ad5764, 16);
static DECLARE_AD5764_CHANNELS(ad5744, 14);
static const struct ad5764_chip_info ad5764_chip_infos[] = {
[ID_AD5744] = {
.int_vref = 0,
.channels = ad5744_channels,
},
[ID_AD5744R] = {
.int_vref = 5000000,
.channels = ad5744_channels,
},
[ID_AD5764] = {
.int_vref = 0,
.channels = ad5764_channels,
},
[ID_AD5764R] = {
.int_vref = 5000000,
.channels = ad5764_channels,
},
};
static int ad5764_write(struct iio_dev *indio_dev, unsigned int reg,
unsigned int val)
{
struct ad5764_state *st = iio_priv(indio_dev);
int ret;
mutex_lock(&st->lock);
st->data[0].d32 = cpu_to_be32((reg << 16) | val);
ret = spi_write(st->spi, &st->data[0].d8[1], 3);
mutex_unlock(&st->lock);
return ret;
}
static int ad5764_read(struct iio_dev *indio_dev, unsigned int reg,
unsigned int *val)
{
struct ad5764_state *st = iio_priv(indio_dev);
int ret;
struct spi_transfer t[] = {
{
.tx_buf = &st->data[0].d8[1],
.len = 3,
.cs_change = 1,
}, {
.rx_buf = &st->data[1].d8[1],
.len = 3,
},
};
mutex_lock(&st->lock);
st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));
ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
if (ret >= 0)
*val = be32_to_cpu(st->data[1].d32) & 0xffff;
mutex_unlock(&st->lock);
return ret;
}
static int ad5764_chan_info_to_reg(struct iio_chan_spec const *chan, long info)
{
switch (info) {
case IIO_CHAN_INFO_RAW:
return AD5764_REG_DATA(chan->address);
case IIO_CHAN_INFO_CALIBBIAS:
return AD5764_REG_OFFSET(chan->address);
case IIO_CHAN_INFO_CALIBSCALE:
return AD5764_REG_FINE_GAIN(chan->address);
default:
break;
}
return 0;
}
static int ad5764_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long info)
{
const int max_val = (1 << chan->scan_type.realbits);
unsigned int reg;
switch (info) {
case IIO_CHAN_INFO_RAW:
if (val >= max_val || val < 0)
return -EINVAL;
val <<= chan->scan_type.shift;
break;
case IIO_CHAN_INFO_CALIBBIAS:
if (val >= 128 || val < -128)
return -EINVAL;
break;
case IIO_CHAN_INFO_CALIBSCALE:
if (val >= 32 || val < -32)
return -EINVAL;
break;
default:
return -EINVAL;
}
reg = ad5764_chan_info_to_reg(chan, info);
return ad5764_write(indio_dev, reg, (u16)val);
}
static int ad5764_get_channel_vref(struct ad5764_state *st,
unsigned int channel)
{
if (st->chip_info->int_vref)
return st->chip_info->int_vref;
else
return regulator_get_voltage(st->vref_reg[channel / 2].consumer);
}
static int ad5764_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long info)
{
struct ad5764_state *st = iio_priv(indio_dev);
unsigned int reg;
int vref;
int ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
reg = AD5764_REG_DATA(chan->address);
ret = ad5764_read(indio_dev, reg, val);
if (ret < 0)
return ret;
*val >>= chan->scan_type.shift;
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBBIAS:
reg = AD5764_REG_OFFSET(chan->address);
ret = ad5764_read(indio_dev, reg, val);
if (ret < 0)
return ret;
*val = sign_extend32(*val, 7);
return IIO_VAL_INT;
case IIO_CHAN_INFO_CALIBSCALE:
reg = AD5764_REG_FINE_GAIN(chan->address);
ret = ad5764_read(indio_dev, reg, val);
if (ret < 0)
return ret;
*val = sign_extend32(*val, 5);
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
/* vout = 4 * vref + ((dac_code / 65536) - 0.5) */
vref = ad5764_get_channel_vref(st, chan->channel);
if (vref < 0)
return vref;
*val = vref * 4 / 1000;
*val2 = chan->scan_type.realbits;
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_OFFSET:
*val = -(1 << chan->scan_type.realbits) / 2;
return IIO_VAL_INT;
}
return -EINVAL;
}
static const struct iio_info ad5764_info = {
.read_raw = ad5764_read_raw,
.write_raw = ad5764_write_raw,
};
static int ad5764_probe(struct spi_device *spi)
{
enum ad5764_type type = spi_get_device_id(spi)->driver_data;
struct iio_dev *indio_dev;
struct ad5764_state *st;
int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (indio_dev == NULL) {
dev_err(&spi->dev, "Failed to allocate iio device\n");
return -ENOMEM;
}
st = iio_priv(indio_dev);
spi_set_drvdata(spi, indio_dev);
st->spi = spi;
st->chip_info = &ad5764_chip_infos[type];
indio_dev->name = spi_g
|