/*
* This file is part of STM32 ADC driver
*
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
* Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
*
* License type: GPLv2
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/iio/timer/stm32-timer-trigger.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include "stm32-adc-core.h"
/* STM32F4 - Registers for each ADC instance */
#define STM32F4_ADC_SR 0x00
#define STM32F4_ADC_CR1 0x04
#define STM32F4_ADC_CR2 0x08
#define STM32F4_ADC_SMPR1 0x0C
#define STM32F4_ADC_SMPR2 0x10
#define STM32F4_ADC_HTR 0x24
#define STM32F4_ADC_LTR 0x28
#define STM32F4_ADC_SQR1 0x2C
#define STM32F4_ADC_SQR2 0x30
#define STM32F4_ADC_SQR3 0x34
#define STM32F4_ADC_JSQR 0x38
#define STM32F4_ADC_JDR1 0x3C
#define STM32F4_ADC_JDR2 0x40
#define STM32F4_ADC_JDR3 0x44
#define STM32F4_ADC_JDR4 0x48
#define STM32F4_ADC_DR 0x4C
/* STM32F4_ADC_SR - bit fields */
#define STM32F4_STRT BIT(4)
#define STM32F4_EOC BIT(1)
/* STM32F4_ADC_CR1 - bit fields */
#define STM32F4_RES_SHIFT 24
#define STM32F4_RES_MASK GENMASK(25, 24)
#define STM32F4_SCAN BIT(8)
#define STM32F4_EOCIE BIT(5)
/* STM32F4_ADC_CR2 - bit fields */
#define STM32F4_SWSTART BIT(30)
#define STM32F4_EXTEN_SHIFT 28
#define STM32F4_EXTEN_MASK GENMASK(29, 28)
#define STM32F4_EXTSEL_SHIFT 24
#define STM32F4_EXTSEL_MASK GENMASK(27, 24)
#define STM32F4_EOCS BIT(10)
#define STM32F4_DDS BIT(9)
#define STM32F4_DMA BIT(8)
#define STM32F4_ADON BIT(0)
#define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
#define STM32_ADC_TIMEOUT_US 100000
#define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
#define STM32_DMA_BUFFER_SIZE PAGE_SIZE
/* External trigger enable */
enum stm32_adc_exten {
STM32_EXTEN_SWTRIG,
STM32_EXTEN_HWTRIG_RISING_EDGE,
STM32_EXTEN_HWTRIG_FALLING_EDGE,
STM32_EXTEN_HWTRIG_BOTH_EDGES,
};
/* extsel - trigger mux selection value */
enum stm32_adc_extsel {
STM32_EXT0,
STM32_EXT1,
STM32_EXT2,
STM32_EXT3,
STM32_EXT4,
STM32_EXT5,
STM32_EXT6,
STM32_EXT7,
STM32_EXT8,
STM32_EXT9,
STM32_EXT10,
STM32_EXT11,
STM32_EXT12,
STM32_EXT13,
STM32_EXT14,
STM32_EXT15,
};
/**
* struct stm32_adc_trig_info - ADC trigger info
* @name: name of the trigger, corresponding to its source
* @extsel: trigger selection
*/
struct stm32_adc_trig_info {
const char *name;
enum stm32_adc_extsel extsel;
};
/**
* stm32_adc_regs - stm32 ADC misc registers & bitfield desc
* @reg: register offset
* @mask: bitfield mask
* @shift: left shift
*/
struct stm32_adc_regs {
int reg;
int mask;
int shift;
};
/**
* struct stm32_adc - private data of each ADC IIO instance
* @common: reference to ADC block common data
* @offset: ADC instance register offset in ADC block
* @completion: end of single conversion completion
* @buffer: data buffer
* @clk: clock for this adc instance
* @irq: interrupt for this adc instance
* @lock: spinlock
* @bufi: data buffer index
* @num_conv: expected number of scan conversions
* @res: data resolution (e.g. RES bitfield value)
* @trigger_polarity: external trigger polarity (e.g. exten)
* @dma_chan: dma channel
* @rx_buf: dma rx buffer cpu address
* @rx_dma_buf: dma rx buffer bus address
* @rx_buf_sz: dma rx buffer size
*/
struct stm32_adc {
struct stm32_adc_common *common;
u32 offset;
struct completion completion;
u16 buffer[STM32_ADC_MAX_SQ];
struct clk *clk;
int irq;
spinlock_t lock; /* interrupt lock */
unsigned int bufi;
unsigned int num_conv;
u32 res;
u32 trigger_polarity;
struct dma_chan *dma_chan;
u8 *rx_buf;
dma_addr_t rx_dma_buf;
unsigned int rx_buf_sz;
};
/**
* struct stm32_adc_chan_spec - specification of stm32 adc channel
* @type: IIO channel type
* @channel: channel number (single ended)
* @name: channel name (single ended)
*/
struct stm32_adc_chan_spec {
enum iio_chan_type type;
int channel;
const char *name;
};
/* Input definitions common for all STM32F4 instances */
static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = {
{ IIO_VOLTAGE, 0, "in0" },
{ IIO_VOLTAGE, 1, "in1" },
{ IIO_VOLTAGE, 2, "in2" },
{ IIO_VOLTAGE, 3, "in3" },
{ IIO_VOLTAGE, 4, "in4" },
{ IIO_VOLTAGE, 5, "in5" },
{ IIO_VOLTAGE, 6, "in6" },
{ IIO_VOLTAGE, 7, "in7" },
{ IIO_VOLTAGE, 8, "in8" <