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/*
* Holt Integrated Circuits HI-8435 threshold detector driver
*
* Copyright (C) 2015 Zodiac Inflight Innovations
* Copyright (C) 2015 Cogent Embedded, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/delay.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_event.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/spi/spi.h>
#include <linux/gpio/consumer.h>
#define DRV_NAME "hi8435"
/* Register offsets for HI-8435 */
#define HI8435_CTRL_REG 0x02
#define HI8435_PSEN_REG 0x04
#define HI8435_TMDATA_REG 0x1E
#define HI8435_GOCENHYS_REG 0x3A
#define HI8435_SOCENHYS_REG 0x3C
#define HI8435_SO7_0_REG 0x10
#define HI8435_SO15_8_REG 0x12
#define HI8435_SO23_16_REG 0x14
#define HI8435_SO31_24_REG 0x16
#define HI8435_SO31_0_REG 0x78
#define HI8435_WRITE_OPCODE 0x00
#define HI8435_READ_OPCODE 0x80
/* CTRL register bits */
#define HI8435_CTRL_TEST 0x01
#define HI8435_CTRL_SRST 0x02
struct hi8435_priv {
struct spi_device *spi;
struct mutex lock;
unsigned long event_scan_mask; /* soft mask/unmask channels events */
unsigned int event_prev_val;
unsigned threshold_lo[2]; /* GND-Open and Supply-Open thresholds */
unsigned threshold_hi[2]; /* GND-Open and Supply-Open thresholds */
u8 reg_buffer[3] ____cacheline_aligned;
};
static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val)
{
reg |= HI8435_READ_OPCODE;
return spi_write_then_read(priv->spi, ®, 1, val, 1);
}
static int hi8435_readw(struct hi8435_priv *priv, u8 reg, u16 *val)
{
int ret;
__be16 be_val;
reg |= HI8435_READ_OPCODE;
ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 2);
*val = be16_to_cpu(be_val);
return ret;
}
static int hi8435_readl(struct hi8435_priv *priv, u8 reg, u32 *val)
{
int ret;
__be32 be_val;
reg |= HI8435_READ_OPCODE;
ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 4);
*val = be32_to_cpu(be_val);
return ret;
}
static int hi8435_writeb(struct hi8435_priv *priv, u8 reg, u8 val)
{
priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE;
priv->reg_buffer[1] = val;
return spi_write(priv->spi, priv->reg_buffer, 2);
}
static int hi8435_writew(struct hi8435_priv *priv, u8 reg, u16 val)
{
priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE;
priv->reg_buffer[1] = (val >> 8) & 0xff;
priv->reg_buffer[2] = val & 0xff;
return spi_write(priv->spi, priv->reg_buffer, 3);
}
static int hi8435_read_event_config(struct iio_dev *idev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir)
{
struct hi8435_priv *priv = iio_priv(idev);
return !!(priv->event_scan_mask & BIT(chan->channel));
}
static int hi8435_write_event_config(struct iio_dev *idev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir, int state)
{
struct hi8435_priv *priv = iio_priv(idev);
priv->event_scan_mask &= ~BIT(chan->channel);
if (state)
priv->event_scan_mask |= BIT(chan->channel);
return 0;
}
static int hi8435_read_event_value(struct iio_dev *idev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int *val, int *val2)
{
struct hi8435_priv *priv = iio_priv(idev);
int ret;
u8 mode, psen;
u16 reg;
ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen);
if (ret < 0)
return ret;
/* Supply-Open or GND-Open sensing mode */
mode = !!(psen & BIT(chan->channel / 8));
ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG :
HI8435_GOCENHYS_REG, ®);
if (ret < 0)
return ret;
if (dir == IIO_EV_DIR_FALLING)
*val = ((reg & 0xff) - (reg >> 8)) / 2;
else if (dir == IIO_EV_DIR_RISING)
*val = ((reg & 0xff) + (reg >> 8)) / 2;
return IIO_VAL_INT;
}
static int hi8435_write_event_value(struct iio_dev *idev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
enum iio_event_info info,
int val, int val2)
{
struct hi8435_priv *priv = iio_priv(idev);
int ret;
u8 mode, psen;
u16 reg;
ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen);
if (ret < 0)
return ret;
/* Supply-Open or GND-Open sensing mode */
mode = !!(psen & BIT(chan->channel / 8));
ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG :
HI8435_GOCENHYS_REG, ®);
if (ret < 0)
return ret;
if (dir == IIO_EV_DIR_FALLING) {
/* falling threshold range 2..21V, hysteresis minimum 2V */
if (val < 2 || val > 21 || (val + 2) > priv->threshold_hi[mode])
return -EINVAL;
if (val == priv->threshold_lo[mode])
return 0;
priv->threshold_lo[mode] = val;
/* hysteresis must not be odd */
if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2)
priv->threshold_hi[mode]--;
} else if (dir == IIO_EV_DIR_RISING) {
/* rising threshold range 3..22V, hysteresis minimum 2V */
if (val < 3 || val > 22 || val < (priv->threshold_lo[mode] + 2))
return -EINVAL;
if (val == priv->threshold_hi[mode])
return 0;
priv->threshold_hi[mode] = val;
/* hysteresis must not be odd */
if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2)
priv->threshold_lo[mode]++;
}
/* program thresholds */
mutex_lock(&priv->lock);
ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG :
HI8435_GOCENHYS_REG,
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