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// SPDX-License-Identifier: GPL-2.0-only
/*
* Analog Devices Generic AXI ADC IP core
* Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
*
* Copyright 2012-2020 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/buffer-dmaengine.h>
#include <linux/fpga/adi-axi-common.h>
#include <linux/iio/adc/adi-axi-adc.h>
/**
* Register definitions:
* https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
*/
/* ADC controls */
#define ADI_AXI_REG_RSTN 0x0040
#define ADI_AXI_REG_RSTN_CE_N BIT(2)
#define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
#define ADI_AXI_REG_RSTN_RSTN BIT(0)
/* ADC Channel controls */
#define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
#define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11)
#define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
#define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9)
#define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8)
#define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
#define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5)
#define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4)
#define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
#define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0)
#define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \
ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
ADI_AXI_REG_CHAN_CTRL_ENABLE)
struct adi_axi_adc_core_info {
unsigned int version;
};
struct adi_axi_adc_state {
struct mutex lock;
struct adi_axi_adc_client *client;
void __iomem *regs;
};
struct adi_axi_adc_client {
struct list_head entry;
struct adi_axi_adc_conv conv;
struct adi_axi_adc_state *state;
struct device *dev;
const struct adi_axi_adc_core_info *info;
};
static LIST_HEAD(registered_clients);
static DEFINE_MUTEX(registered_clients_lock);
static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv)
{
return container_of(conv, struct adi_axi_adc_client, conv);
}
void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)
{
struct adi_axi_adc_client *cl = conv_to_client(conv);
return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN);
}
EXPORT_SYMBOL_GPL(adi_axi_adc_conv_priv);
static void adi_axi_adc_write(struct adi_axi_adc_state *st,
unsigned int reg,
unsigned int val)
{
iowrite32(val, st->regs + reg);
}
static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st,
unsigned int reg)
{
return ioread32(st->regs + reg);
}
static int adi_axi_adc_config_dma_buffer(struct device *dev,
struct iio_dev *indio_dev)
{
struct iio_buffer *buffer;
const char *dma_name;
if (!device_property_present(dev, "dmas"))
return 0;
if (device_property_read_string(dev, "dma-names", &dma_name))
dma_name = "rx";
buffer = devm_iio_dmaengine_buffer_alloc(indio_dev->dev.parent,
dma_name);
if (IS_ERR(buffer))
return PTR_ERR(buffer);
indio_dev->modes |= INDIO_BUFFER_HARDWARE;
iio_device_attach_buffer(indio_dev, buffer);
return 0;
}
static int adi_axi_adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct adi_axi_adc_state *st = iio_priv(indio_dev);
struct adi_axi_adc_conv *conv = &st->client->conv;
if (!conv->read_raw)
return -EOPNOTSUPP;
return conv->read_raw(conv, chan, val, val2, mask);
}
static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct adi_axi_adc_state *st = iio_priv(indio_dev);
struct adi_axi_adc_conv *conv = &st->client->conv;
if (!conv->write_raw)
return -EOPNOTSUPP;
return conv->write_raw(conv, chan, val, val2, mask);
}
static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,
const unsigned long *scan_mask)
{
struct adi_axi_adc_state *st = iio_priv(indio_dev);
struct adi_axi_adc_conv *conv = &st->client->conv;
unsigned int i, ctrl;
for (i = 0; i < conv->chip_info->num_channels; i++) {
ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i));
if (test_bit(i, scan_mask))
ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE;
else
ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE;
adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl);
}
return 0;
}
static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev,
size_t sizeof_priv)
{
struct adi_axi_adc_client *cl;
size_t alloc_size;
alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN);
if (sizeof_priv)
alloc_size += ALIGN(sizeof_priv, IIO_ALIGN);
cl = kzalloc(alloc_size, GFP_KERNEL);
if (!cl)
return ERR_PTR(-ENOMEM);
mutex_lock(®istered_clients_lock);
cl->dev = get_device(dev);
list_add_tail(&cl->entry, ®istered_clients);
mutex_unlock(®istered_clients_lock);
return &cl->conv;
}
static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv)
{
struct adi_axi_adc_client *cl = conv_to_client(conv);
mutex_lock(®istered_clients_lock);
list_del(&cl->entry);
put_device(cl->dev);
mutex_unlock(®istered_clients_lock);
kfree(cl);
}
static void devm_adi_axi_adc_conv_release(struct device *dev, void *res)
{
adi_axi_adc_conv_unregister(*(struct adi_axi_adc_conv **)res);
}
struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
size_t sizeof_priv)
{
struct adi_axi_adc_conv **ptr, *conv;
ptr = devres_alloc(devm_adi_axi_adc_conv_release, sizeof(*ptr),
GFP_KERNEL);
if (!ptr)
return ERR_PTR(-ENOMEM);
conv = adi_axi_adc_conv_register(dev, sizeof_priv);
if (IS_ERR(conv)) {
devres_free(ptr);
return ERR_CAST(conv);
}
*ptr = conv;
devres_add(dev, ptr);
return conv;
}
EXPORT_SYMBOL_GPL(devm_adi_axi_adc_conv_register);
static ssize_t in_voltage_scale_available_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct adi_axi_adc_state *st = iio_priv(indio_dev);
struct adi_axi_adc_conv *conv = &st->client->conv;
size_t len = 0;
int i;
for (i = 0; i < conv->chip_info->num_scales; i++) {
const unsigned int *s = conv->chip_info->scale_table[i];
len += scnprintf(buf + len, PAGE_SIZE - len,
"%u.%06u ", s[0], s[1]);
}
buf[len - 1] = '\n';
return len;
}
static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0);
enum {
ADI_AXI_ATTR_SCALE_AVAIL,
};
#define ADI_AXI_ATTR(_en_, _file_) \
[ADI_AXI_ATTR_##_en_] = &iio_dev_attr_##_file_.dev_attr.attr
static struct attribute *adi_axi_adc_attributes[] = {
ADI_AXI_ATTR(SCALE_AVAIL, in_voltage_scale_available),
NULL
};
static umode_t axi_adc_attr_is_visible(struct kobject
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