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|
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/iopoll.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#define UNIPHIER_FI2C_CR 0x00 /* control register */
#define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */
#define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */
#define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */
#define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */
#define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */
#define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */
#define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */
#define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */
#define UNIPHIER_FI2C_SLAD 0x0c /* slave address */
#define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */
#define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */
#define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */
#define UNIPHIER_FI2C_DSUT 0x1c /* data setup time control */
#define UNIPHIER_FI2C_INT 0x20 /* interrupt status */
#define UNIPHIER_FI2C_IE 0x24 /* interrupt enable */
#define UNIPHIER_FI2C_IC 0x28 /* interrupt clear */
#define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */
#define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */
#define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */
#define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */
#define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */
#define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */
#define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */
#define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */
#define UNIPHIER_FI2C_SR 0x2c /* status register */
#define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */
#define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */
#define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */
#define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */
#define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */
#define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */
#define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */
#define UNIPHIER_FI2C_RST 0x34 /* reset control */
#define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */
#define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */
#define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */
#define UNIPHIER_FI2C_BM 0x38 /* bus monitor */
#define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */
#define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */
#define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */
#define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */
#define UNIPHIER_FI2C_NOISE 0x3c /* noise filter control */
#define UNIPHIER_FI2C_TBC 0x40 /* TX byte count setting */
#define UNIPHIER_FI2C_RBC 0x44 /* RX byte count setting */
#define UNIPHIER_FI2C_TBCM 0x48 /* TX byte count monitor */
#define UNIPHIER_FI2C_RBCM 0x4c /* RX byte count monitor */
#define UNIPHIER_FI2C_BRST 0x50 /* bus reset */
#define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */
#define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */
#define UNIPHIER_FI2C_INT_FAULTS \
(UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL)
#define UNIPHIER_FI2C_INT_STOP \
(UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC)
#define UNIPHIER_FI2C_RD BIT(0)
#define UNIPHIER_FI2C_STOP BIT(1)
#define UNIPHIER_FI2C_MANUAL_NACK BIT(2)
#define UNIPHIER_FI2C_BYTE_WISE BIT(3)
#define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4)
#define UNIPHIER_FI2C_DEFAULT_SPEED 100000
#define UNIPHIER_FI2C_MAX_SPEED 400000
#define UNIPHIER_FI2C_FIFO_SIZE 8
struct uniphier_fi2c_priv {
struct completion comp;
struct i2c_adapter adap;
void __iomem *membase;
struct clk *clk;
unsigned int len;
u8 *buf;
u32 enabled_irqs;
int error;
unsigned int flags;
unsigned int busy_cnt;
unsigned int clk_cycle;
spinlock_t lock; /* IRQ synchronization */
};
static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
bool first)
{
int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
/*
* TX-FIFO stores slave address in it for the first access.
* Decrement the counter.
*/
if (first)
fifo_space--;
while (priv->len) {
if (fifo_space-- <= 0)
break;
dev_dbg(&priv->adap.dev, "write data: %02x\n", *priv->buf);
writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);
priv->len--;
}
}
static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv)
{
int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ?
1 : UNIPHIER_FI2C_FIFO_SIZE;
while (priv->len) {
if (fifo_left-- <= 0)
break;
*priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX);
dev_dbg(&priv->adap.dev, "read data: %02x\n", priv->buf[-1]);
priv->len--;
}
}
static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv)
{
writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);
}
static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv,
u32 mask)
{
writel(mask, priv->membase + UNIPHIER_FI2C_IC);
}
static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv)
{
dev_dbg(&priv->adap.dev, "stop condition\n");
priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP;
uniphier_fi2c_set_irqs(priv);
writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO,
priv->membase + UNIPHIER_FI2C_CR);
}
static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id)
{
struct uniphier_fi2c_priv *priv = dev_id;
u32 irq_status;
spin_lock(&priv->lock);
irq_status = readl(priv->membase + UNIPHIER_FI2C_INT);
irq_status &= priv->enabled_irqs;
dev_dbg(&priv->adap.dev,
"interrupt: enabled_irqs=%04x, irq_status=%04x\n",
priv->enabled_irqs, irq_status);
if (irq_status & UNIPHIER_FI2C_INT_STOP)
goto complete;
if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) {
dev_dbg(&priv->adap.dev, "arbitration lost\n");
priv->error = -EAGAIN;
goto complete;
}
if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) {
dev_dbg(&priv->adap.dev, "could not get ACK\n");
priv->error = -ENXIO;
if (priv->flags & UNIPHIER_FI2C_RD) {
/*
* work around a hardware bug:
* The receive-completed interrupt is never set even if
* STOP condition is detected after the address phase
* of read transaction fails to get ACK.
* To avoid time-out error, we issue STOP here,
* but do not wait for its completion.
* It should be checked after exiting this handler.
*/
uniphier_fi2c_stop(priv);
priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP;
goto complete;
}
goto stop;
}
if (irq_status & UNIPHIER_FI2C_INT_TE) {
if (!priv->len)
goto data_done;
uniphier_fi2c_fill_txfifo(priv, false);
goto handled;
}
if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) {
uniphier_fi2c_drain_rxfifo(priv);
/*
* If the number of bytes to read is multiple of the FIFO size
* (msg->len == 8, 16, 24, ...), the INT_RF bit is set a little
* earlier than INT_RB. We wait for INT_RB to confirm the
* completion of the current message.
*/
if (!priv->len && (irq_status & UNIPHIER_FI2C_INT_RB))
goto data_done;
if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) {
if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE &&
!(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) {
dev_dbg(&priv->adap.dev,
"enable read byte count IRQ\n");
priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB;
uniphier_fi2c_set_irqs(priv);
priv->flags |= UNIPHIER_FI2C_BYTE_WISE;
}
if (priv->len <= 1) {
dev_dbg(&priv->adap.dev, "set NACK\n");
writel(UNIPHIER_FI2C_CR_MST |
UNIPHIER_FI2C_CR_NACK,
priv->membase + UNIPHIER_FI2C_CR);
}
}
goto handled;
}
spin_unlock(&priv->lock);
return IRQ_NONE;
data_done:
if (priv->flags & UNIPHIER_FI2C_STOP) {
stop:
uniphier_fi2c_stop(priv);
} else {
complete:
priv->enabled_irqs = 0;
uniphier_fi2c_set_irqs
|