1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2012 FUJITSU SEMICONDUCTOR LIMITED
*/
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#define WAIT_PCLK(n, rate) \
ndelay(DIV_ROUND_UP(DIV_ROUND_UP(1000000000, rate), n) + 10)
/* I2C register address definitions */
#define SYNQUACER_I2C_REG_BSR (0x00 << 2) // Bus Status
#define SYNQUACER_I2C_REG_BCR (0x01 << 2) // Bus Control
#define SYNQUACER_I2C_REG_CCR (0x02 << 2) // Clock Control
#define SYNQUACER_I2C_REG_ADR (0x03 << 2) // Address
#define SYNQUACER_I2C_REG_DAR (0x04 << 2) // Data
#define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS
#define SYNQUACER_I2C_REG_FSR (0x06 << 2) // Bus Clock Freq
#define SYNQUACER_I2C_REG_BC2R (0x07 << 2) // Bus Control 2
/* I2C register bit definitions */
#define SYNQUACER_I2C_BSR_FBT BIT(0) // First Byte Transfer
#define SYNQUACER_I2C_BSR_GCA BIT(1) // General Call Address
#define SYNQUACER_I2C_BSR_AAS BIT(2) // Address as Slave
#define SYNQUACER_I2C_BSR_TRX BIT(3) // Transfer/Receive
#define SYNQUACER_I2C_BSR_LRB BIT(4) // Last Received Bit
#define SYNQUACER_I2C_BSR_AL BIT(5) // Arbitration Lost
#define SYNQUACER_I2C_BSR_RSC BIT(6) // Repeated Start Cond.
#define SYNQUACER_I2C_BSR_BB BIT(7) // Bus Busy
#define SYNQUACER_I2C_BCR_INT BIT(0) // Interrupt
#define SYNQUACER_I2C_BCR_INTE BIT(1) // Interrupt Enable
#define SYNQUACER_I2C_BCR_GCAA BIT(2) // Gen. Call Access Ack.
#define SYNQUACER_I2C_BCR_ACK BIT(3) // Acknowledge
#define SYNQUACER_I2C_BCR_MSS BIT(4) // Master Slave Select
#define SYNQUACER_I2C_BCR_SCC BIT(5) // Start Condition Cont.
#define SYNQUACER_I2C_BCR_BEIE BIT(6) // Bus Error Int Enable
#define SYNQUACER_I2C_BCR_BER BIT(7) // Bus Error
#define SYNQUACER_I2C_CCR_CS_MASK (0x1f) // CCR Clock Period Sel.
#define SYNQUACER_I2C_CCR_EN BIT(5) // Enable
#define SYNQUACER_I2C_CCR_FM BIT(6) // Speed Mode Select
#define SYNQUACER_I2C_CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
#define SYNQUACER_I2C_BC2R_SCLL BIT(0) // SCL Low Drive
#define SYNQUACER_I2C_BC2R_SDAL BIT(1) // SDA Low Drive
#define SYNQUACER_I2C_BC2R_SCLS BIT(4) // SCL Status
#define SYNQUACER_I2C_BC2R_SDAS BIT(5) // SDA Status
/* PCLK frequency */
#define SYNQUACER_I2C_BUS_CLK_FR(rate) (((rate) / 20000000) + 1)
/* STANDARD MODE frequency */
#define SYNQUACER_I2C_CLK_MASTER_STD(rate) \
DIV_ROUND_UP(DIV_ROUND_UP((rate), 100000) - 2, 2)
/* FAST MODE frequency */
#define SYNQUACER_I2C_CLK_MASTER_FAST(rate) \
DIV_ROUND_UP((DIV_ROUND_UP((rate), 400000) - 2) * 2, 3)
/* (clkrate <= 18000000) */
/* calculate the value of CS bits in CCR register on standard mode */
#define SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rate) \
((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
& SYNQUACER_I2C_CCR_CS_MASK)
/* calculate the value of CS bits in CSR register on standard mode */
#define SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rate) 0x00
/* calculate the value of CS bits in CCR register on fast mode */
#define SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rate) \
((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
& SYNQUACER_I2C_CCR_CS_MASK)
/* calculate the value of CS bits in CSR register on fast mode */
#define SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rate) 0x00
/* (clkrate > 18000000) */
/* calculate the value of CS bits in CCR register on standard mode */
#define SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rate) \
((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) \
& SYNQUACER_I2C_CCR_CS_MASK)
/* calculate the value of CS bits in CSR register on standard mode */
#define SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rate) \
(((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) >> 5) \
& SYNQUACER_I2C_CSR_CS_MASK)
/* calculate the value of CS bits in CCR register on fast mode */
#define SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rate) \
((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
& SYNQUACER_I2C_CCR_CS_MASK)
/* calculate the value of CS bits in CSR register on fast mode */
#define SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rate) \
(((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) >> 5) \
& SYNQUACER_I2C_CSR_CS_MASK)
/* min I2C clock frequency 14M */
#define SYNQUACER_I2C_MIN_CLK_RATE (14 * 1000000)
/* max I2C clock frequency 200M */
#define SYNQUACER_I2C_MAX_CLK_RATE (200 * 1000000)
/* I2C clock frequency 18M */
#define SYNQUACER_I2C_CLK_RATE_18M (18 * 1000000)
#define SYNQUACER_I2C_SPEED_FM 400 // Fast Mode
#define SYNQUACER_I2C_SPEED_SM 100 // Standard Mode
enum i2c_state {
STATE_IDLE,
STATE_START,
STATE_READ,
STATE_WRITE
};
struct synquacer_i2c {
struct completion completion;
struct i2c_msg *msg;
u32 msg_num;
u32 msg_idx;
u32 msg_ptr;
int irq;
struct device *dev;
void __iomem *base;
struct clk *pclk;
u32 pclkrate;
u32 speed_khz;
u32 timeout_ms;
enum i2c_state state;
struct i2c_adapter adapter;
bool is_suspended;
};
static inline int is_lastmsg(struct synquacer_i2c *i2c)
{
return i2c->msg_idx >= (i2c->msg_num - 1);
}
static inline int is_msglast(struct synquacer_i2c *i2c)
{
return i2c->msg_ptr == (i2c->msg->len - 1);
}
static inline int is_msgend(struct synquacer_i2c *i2c)
{
return i2c->msg_ptr >= i2c->msg->len;
}
static inline unsigned long calc_timeout_ms(struct synquacer_i2c *i2c,
struct i2c_msg *msgs,
int num)
{
unsigned long bit_count = 0;
int i;
for (i = 0; i < num; i++, msgs++)
bit_count += msgs->len;
return DIV_ROUND_UP((bit_count * 9 + num * 10) * 3, 200) + 10;
}
static void synquacer_i2c_stop(struct synquacer_i2c *i2c, int ret)
{
/*
* clear IRQ (INT=0, BER=0)
* set Stop Condition (MSS=0)
* Interrupt Disable
*/
writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
i2c->state = STATE_IDLE;
i2c->msg_ptr = 0;
i2c->msg = NULL;
i2c->msg_idx++;
i2c->msg_num = 0;
if (ret)
i2c->msg_idx = ret;
complete(&i2c->completion);
}
static void synquacer_i2c_hw_init(struct synquacer_i2c *i2c)
{
unsigned char ccr_cs, csr_cs;
u32 rt = i2c->pclkrate;
/* Set own Address */
writeb(0, i2c->base + SYNQUACER_I2C_REG_ADR);
/* Set PCLK frequency */
writeb(SYNQUACER_I2C_BUS_CLK_FR(i2c->pclkrate),
i2c->base + SYNQUACER_I2C_REG_FSR);
switch (i2c->speed_khz) {
case SYNQUACER_I2C_SPEED_FM:
if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rt);
csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rt);
} else {
ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rt);
csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rt);
}
/* Set Clock and enable, Set fast mode */
writeb(ccr_cs | SYNQUACER_I2C_CCR_FM |
SYNQUACER_I2C_CCR_EN,
i2c->base + SYNQUACER_I2C_REG_CCR);
writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
break;
case SYNQUACER_I2C_SPEED_SM:
if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rt);
csr_cs = SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rt);
} else {
ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rt);
csr_cs = SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rt);
}
/* Set Clock and enable, Set standard mode */
writeb(ccr_cs | SYNQUACER_I2C_CCR_EN,
i2c->base + SYNQUACER_I2C_REG_CCR);
writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
break;
default:
WARN_ON(1);
}
/* clear IRQ (INT=0, BER=0), Interrupt Disable */
writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
writeb(0, i2c->base + SYNQUACER_I2C_REG_BC2R);
}
static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c)
{
/* Disable clock */
writeb(0, i2c->base + SYNQUACER_I2C_REG_CCR);
writeb(0, i2c->base + SYNQUACER_I2C_REG_CSR);
WAIT_PCLK(100, i2c->pclkrate);
}
static int synquacer_i2c_master_start(struct synquacer_i2c *i2c,
struct i2c_msg *pmsg)
{
unsigned char bsr, bcr;
writeb(i2c_8bit_addr_from_msg(pmsg), i2c->base + SYNQUACER_I2C_REG_DAR);
dev_dbg(i2c->dev, "slave:0x%02x\n", pmsg->addr);
/* Generate Start Condition */
bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr
|