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/*
* Copyright (C) 2013 STMicroelectronics
*
* I2C master mode controller driver, used in STMicroelectronics devices.
*
* Author: Maxime Coquelin <maxime.coquelin@st.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
/* SSC registers */
#define SSC_BRG 0x000
#define SSC_TBUF 0x004
#define SSC_RBUF 0x008
#define SSC_CTL 0x00C
#define SSC_IEN 0x010
#define SSC_STA 0x014
#define SSC_I2C 0x018
#define SSC_SLAD 0x01C
#define SSC_REP_START_HOLD 0x020
#define SSC_START_HOLD 0x024
#define SSC_REP_START_SETUP 0x028
#define SSC_DATA_SETUP 0x02C
#define SSC_STOP_SETUP 0x030
#define SSC_BUS_FREE 0x034
#define SSC_TX_FSTAT 0x038
#define SSC_RX_FSTAT 0x03C
#define SSC_PRE_SCALER_BRG 0x040
#define SSC_CLR 0x080
#define SSC_NOISE_SUPP_WIDTH 0x100
#define SSC_PRSCALER 0x104
#define SSC_NOISE_SUPP_WIDTH_DATAOUT 0x108
#define SSC_PRSCALER_DATAOUT 0x10c
/* SSC Control */
#define SSC_CTL_DATA_WIDTH_9 0x8
#define SSC_CTL_DATA_WIDTH_MSK 0xf
#define SSC_CTL_BM 0xf
#define SSC_CTL_HB BIT(4)
#define SSC_CTL_PH BIT(5)
#define SSC_CTL_PO BIT(6)
#define SSC_CTL_SR BIT(7)
#define SSC_CTL_MS BIT(8)
#define SSC_CTL_EN BIT(9)
#define SSC_CTL_LPB BIT(10)
#define SSC_CTL_EN_TX_FIFO BIT(11)
#define SSC_CTL_EN_RX_FIFO BIT(12)
#define SSC_CTL_EN_CLST_RX BIT(13)
/* SSC Interrupt Enable */
#define SSC_IEN_RIEN BIT(0)
#define SSC_IEN_TIEN BIT(1)
#define SSC_IEN_TEEN BIT(2)
#define SSC_IEN_REEN BIT(3)
#define SSC_IEN_PEEN BIT(4)
#define SSC_IEN_AASEN BIT(6)
#define SSC_IEN_STOPEN BIT(7)
#define SSC_IEN_ARBLEN BIT(8)
#define SSC_IEN_NACKEN BIT(10)
#define SSC_IEN_REPSTRTEN BIT(11)
#define SSC_IEN_TX_FIFO_HALF BIT(12)
#define SSC_IEN_RX_FIFO_HALF_FULL BIT(14)
/* SSC Status */
#define SSC_STA_RIR BIT(0)
#define SSC_STA_TIR BIT(1)
#define SSC_STA_TE BIT(2)
#define SSC_STA_RE BIT(3)
#define SSC_STA_PE BIT(4)
#define SSC_STA_CLST BIT(5)
#define SSC_STA_AAS BIT(6)
#define SSC_STA_STOP BIT(7)
#define SSC_STA_ARBL BIT(8)
#define SSC_STA_BUSY BIT(9)
#define SSC_STA_NACK BIT(10)
#define SSC_STA_REPSTRT BIT(11)
#define SSC_STA_TX_FIFO_HALF BIT(12)
#define SSC_STA_TX_FIFO_FULL BIT(13)
#define SSC_STA_RX_FIFO_HALF BIT(14)
/* SSC I2C Control */
#define SSC_I2C_I2CM BIT(0)
#define SSC_I2C_STRTG BIT(1)
#define SSC_I2C_STOPG BIT(2)
#define SSC_I2C_ACKG BIT(3)
#define SSC_I2C_AD10 BIT(4)
#define SSC_I2C_TXENB BIT(5)
#define SSC_I2C_REPSTRTG BIT(11)
#define SSC_I2C_SLAVE_DISABLE BIT(12)
/* SSC Tx FIFO Status */
#define SSC_TX_FSTAT_STATUS 0x07
/* SSC Rx FIFO Status */
#define SSC_RX_FSTAT_STATUS 0x07
/* SSC Clear bit operation */
#define SSC_CLR_SSCAAS BIT(6)
#define SSC_CLR_SSCSTOP BIT(7)
#define SSC_CLR_SSCARBL BIT(8)
#define SSC_CLR_NACK BIT(10)
#define SSC_CLR_REPSTRT BIT(11)
/* SSC Clock Prescaler */
#define SSC_PRSC_VALUE 0x0f
#define SSC_TXFIFO_SIZE 0x8
#define SSC_RXFIFO_SIZE 0x8
enum st_i2c_mode {
I2C_MODE_STANDARD,
I2C_MODE_FAST,
I2C_MODE_END,
};
/**
* struct st_i2c_timings - per-Mode tuning parameters
* @rate: I2C bus rate
* @rep_start_hold: I2C repeated start hold time requirement
* @rep_start_setup: I2C repeated start set up time requirement
* @start_hold: I2C start hold time requirement
* @data_setup_time: I2C data set up time requirement
* @stop_setup_time: I2C stop set up time requirement
* @bus_free_time: I2C bus free time requirement
* @sda_pulse_min_limit: I2C SDA pulse mini width limit
*/
struct st_i2c_timings {
u32 rate;
u32 rep_start_hold;
u32 rep_start_setup;
u32 start_hold;
u32 data_setup_time;
u32 stop_setup_time;
u32 bus_free_time;
u32 sda_pulse_min_limit;
};
/**
* struct st_i2c_client - client specific data
* @addr: 8-bit slave addr, including r/w bit
* @count: number of bytes to be transfered
* @xfered: number of bytes already transferred
* @buf: data buffer
* @result: result of the transfer
* @stop: last I2C msg to be sent, i.e. STOP to be generated
*/
struct st_i2c_client {
u8 addr;
u32 count;
u32 xfered;
u8 *buf;
int result;
bool stop;
};
/**
* struct st_i2c_dev - private data of the controller
* @adap: I2C adapter for this controller
* @dev: device for this controller
* @base: virtual memory area
* @complete: completion of I2C message
* @irq: interrupt line for th controller
* @clk: hw ssc block clock
* @mode: I2C mode of the controller. Standard or Fast only supported
* @scl_min_width_us: SCL line minimum pulse width in us
* @sda_min_width_us: SDA line minimum pulse width in us
* @client: I2C transfert information
* @busy: I2C transfer on-going
*/
struct st_i2c_dev {
struct i2c_adapter adap;
struct device *dev;
void __iomem *base;
struct completion complete;
int irq;
struct clk *clk;
int mode;
u32 scl_min_width_us;
u32 sda_min_width_us;
struct st_i2c_client client;
bool busy;
};
static inline void st_i2c_set_bits(void __iomem *reg, u32 mask)
{
writel_relaxed(readl_relaxed(reg) | mask, reg);
}
static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask)
{
writel_relaxed(readl_relaxed(reg) & ~mask, reg);
}
/* From I2C Specifications v0.5 */
static struct st_i2c_timings i2c_timings[] = {
[I2C_MODE_STANDARD] = {
.rate = 100000,
.rep_start_hold = 4000,
.rep_start_setup = 4700,
.start_hold = 4000,
.data_setup_time = 250,
.stop_setup_time = 4000,
.bus_free_time = 4700,
},
[I2C_MODE_FAST] = {
.rate = 400000,
.rep_start_hold = 600,
.rep_start_setup = 600,
.start_hold = 600,
.data_setup_time = 100,
.stop_setup_time = 600,
.bus_free_time = 1300,
},
};
static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev)
{
int count, i;
/*
* Counter only counts up to 7 but fifo size is 8...
* When fifo is full, counter is 0 and RIR bit of status register is
* set
*/
if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR)
count = SSC_RXFIFO_SIZE;
else
count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) &
SSC_RX_FSTAT_STATUS;
for (i = 0; i < count; i++)
readl_relaxed(i2c_dev->base + SSC_RBUF);
}
static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev)
{
/*
* FIFO needs to be emptied before reseting the IP,
* else the controller raises a BUSY error.
*/
st_i2c_flush_rx_fifo(i2c_dev);
st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
}
/**
* st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings
* @i2c_dev: Controller's private data
*/
static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev)
{
unsigned long rate;
u32 val, ns_per_clk;
struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode];
st_i2c_soft_reset(i2c_dev);
val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL |
SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP;
writel_relaxed(val, i2c_dev->base + SSC_CLR);
/* SSC Control register setup */
val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9;
writel_relaxed(val, i2c_dev->base +
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