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/*
* Copyright (C) 2017 Spreadtrum Communications Inc.
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#define I2C_CTL 0x00
#define I2C_ADDR_CFG 0x04
#define I2C_COUNT 0x08
#define I2C_RX 0x0c
#define I2C_TX 0x10
#define I2C_STATUS 0x14
#define I2C_HSMODE_CFG 0x18
#define I2C_VERSION 0x1c
#define ADDR_DVD0 0x20
#define ADDR_DVD1 0x24
#define ADDR_STA0_DVD 0x28
#define ADDR_RST 0x2c
/* I2C_CTL */
#define STP_EN BIT(20)
#define FIFO_AF_LVL_MASK GENMASK(19, 16)
#define FIFO_AF_LVL 16
#define FIFO_AE_LVL_MASK GENMASK(15, 12)
#define FIFO_AE_LVL 12
#define I2C_DMA_EN BIT(11)
#define FULL_INTEN BIT(10)
#define EMPTY_INTEN BIT(9)
#define I2C_DVD_OPT BIT(8)
#define I2C_OUT_OPT BIT(7)
#define I2C_TRIM_OPT BIT(6)
#define I2C_HS_MODE BIT(4)
#define I2C_MODE BIT(3)
#define I2C_EN BIT(2)
#define I2C_INT_EN BIT(1)
#define I2C_START BIT(0)
/* I2C_STATUS */
#define SDA_IN BIT(21)
#define SCL_IN BIT(20)
#define FIFO_FULL BIT(4)
#define FIFO_EMPTY BIT(3)
#define I2C_INT BIT(2)
#define I2C_RX_ACK BIT(1)
#define I2C_BUSY BIT(0)
/* ADDR_RST */
#define I2C_RST BIT(0)
#define I2C_FIFO_DEEP 12
#define I2C_FIFO_FULL_THLD 15
#define I2C_FIFO_EMPTY_THLD 4
#define I2C_DATA_STEP 8
#define I2C_ADDR_DVD0_CALC(high, low) \
((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))
#define I2C_ADDR_DVD1_CALC(high, low) \
(((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))
/* timeout (ms) for pm runtime autosuspend */
#define SPRD_I2C_PM_TIMEOUT 1000
/* SPRD i2c data structure */
struct sprd_i2c {
struct i2c_adapter adap;
struct device *dev;
void __iomem *base;
struct i2c_msg *msg;
struct clk *clk;
u32 src_clk;
u32 bus_freq;
struct completion complete;
u8 *buf;
u32 count;
int irq;
int err;
};
static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count)
{
writel(count, i2c_dev->base + I2C_COUNT);
}
static void sprd_i2c_send_stop(struct sprd_i2c *i2c_dev, int stop)
{
u32 tmp = readl(i2c_dev->base + I2C_CTL);
if (stop)
writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL);
else
writel(tmp | STP_EN, i2c_dev->base + I2C_CTL);
}
static void sprd_i2c_clear_start(struct sprd_i2c *i2c_dev)
{
u32 tmp = readl(i2c_dev->base + I2C_CTL);
writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL);
}
static void sprd_i2c_clear_ack(struct sprd_i2c *i2c_dev)
{
u32 tmp = readl(i2c_dev->base + I2C_STATUS);
writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS);
}
static void sprd_i2c_clear_irq(struct sprd_i2c *i2c_dev)
{
u32 tmp = readl(i2c_dev->base + I2C_STATUS);
writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS);
}
static void sprd_i2c_reset_fifo(struct sprd_i2c *i2c_dev)
{
writel(I2C_RST, i2c_dev->base + ADDR_RST);
}
static void sprd_i2c_set_devaddr(struct sprd_i2c *i2c_dev, struct i2c_msg *m)
{
writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG);
}
static void sprd_i2c_write_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
{
u32 i;
for (i = 0; i < len; i++)
writeb(buf[i], i2c_dev->base + I2C_TX);
}
static void sprd_i2c_read_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
{
u32 i;
for (i = 0; i < len; i++)
buf[i] = readb(i2c_dev->base + I2C_RX);
}
static void sprd_i2c_set_full_thld(struct sprd_i2c *i2c_dev, u32 full_thld)
{
u32 tmp = readl(i2c_dev->base + I2C_CTL);
tmp &= ~FIFO_AF_LVL_MASK;
tmp |= full_thld << FIFO_AF_LVL;
writel(tmp, i2c_dev->base + I2C_CTL);
};
static void sprd_i2c_set_empty_thld(struct sprd_i2c *i2c_dev, u32 empty_thld)
{
u32 tmp = readl(i2c_dev->base + I2C_CTL);
tmp &= ~FIFO_AE_LVL_MASK;
tmp |= empty_thld << FIFO_AE_LVL;
writel(tmp, i2c_dev->base + I2C_CTL);
};
static void sprd_i2c_set_fifo_full_int(struct sprd_i2c *i2c_dev, int enable)
{
u32 tmp = readl(i2c_dev->base + I2C_CTL);
if (enable)
tmp |= FULL_INTEN;
else
tmp &= ~FULL_INTEN;
writel(tmp, i2c_dev->base + I2C_CTL);
};
static void sprd_i2c_set_fifo_empty_int(struct sprd_i2c *i2c_dev, int enable)
{
u32 tmp = readl(i2c_dev->base + I2C_CTL);
if (enable)
tmp |= EMPTY_INTEN;
else
tmp &= ~EMPTY_INTEN;
writel(tmp, i2c_dev->base + I2C_CTL);
};
static void sprd_i2c_opt_start(struct sprd_i2c *i2c_dev)
{
u32 tmp = readl(i2c_dev->base + I2C_CTL);
writel(tmp | I2C_START, i2c_dev->base + I2C_CTL);
}
static void sprd_i2c_opt_mode(struct sprd_i2c *i2c_dev, int rw)
{
u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE;
writel(cmd | rw << 3, i2c_dev->base + I2C_CTL);
}
static void sprd_i2c_data_transfer(struct sprd_i2c *i2c_dev)
{
u32 i2c_count = i2c_dev->count;
u32 need_tran = i2c_count <= I2C_FIFO_DEEP ? i2c_count : I2C_FIFO_DEEP;
struct i2c_msg *msg = i2c_dev->msg;
if (msg->flags & I2C_M_RD) {
sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, I2C_FIFO_FULL_THLD);
i2c_dev->count -= I2C_FIFO_FULL_THLD;
i2c_dev->buf += I2C_FIFO_FULL_THLD;
/*
* If the read data count is larger than rx fifo full threshold,
* we should enable the rx fifo full interrupt to read data
* again.
*/
if (i2c_dev->count >= I2C_FIFO_FULL_THLD)
sprd_i2c_set_fifo_full_int(i2c_dev, 1);
} else {
sprd_i2c_write_bytes(i2c_dev, i2c_dev->buf, need_tran);
i2c_dev->buf += need_tran;
i2c_dev->count -= need_tran;
/*
* If the write data count is arger than tx fifo depth which
* means we can not write all data in one time, then we should
* enable the tx fifo empty interrupt to write again.
*/
if (i2c_count > I2C_FIFO_DEEP)
sprd_i2c_set_fifo_empty_int
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