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/*
* I2C bus driver for the SH7760 I2C Interfaces.
*
* (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
*
* licensed under the terms outlined in the file COPYING.
*
*/
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/module.h>
#include <asm/clock.h>
#include <asm/i2c-sh7760.h>
/* register offsets */
#define I2CSCR 0x0 /* slave ctrl */
#define I2CMCR 0x4 /* master ctrl */
#define I2CSSR 0x8 /* slave status */
#define I2CMSR 0xC /* master status */
#define I2CSIER 0x10 /* slave irq enable */
#define I2CMIER 0x14 /* master irq enable */
#define I2CCCR 0x18 /* clock dividers */
#define I2CSAR 0x1c /* slave address */
#define I2CMAR 0x20 /* master address */
#define I2CRXTX 0x24 /* data port */
#define I2CFCR 0x28 /* fifo control */
#define I2CFSR 0x2C /* fifo status */
#define I2CFIER 0x30 /* fifo irq enable */
#define I2CRFDR 0x34 /* rx fifo count */
#define I2CTFDR 0x38 /* tx fifo count */
#define REGSIZE 0x3C
#define MCR_MDBS 0x80 /* non-fifo mode switch */
#define MCR_FSCL 0x40 /* override SCL pin */
#define MCR_FSDA 0x20 /* override SDA pin */
#define MCR_OBPC 0x10 /* override pins */
#define MCR_MIE 0x08 /* master if enable */
#define MCR_TSBE 0x04
#define MCR_FSB 0x02 /* force stop bit */
#define MCR_ESG 0x01 /* en startbit gen. */
#define MSR_MNR 0x40 /* nack received */
#define MSR_MAL 0x20 /* arbitration lost */
#define MSR_MST 0x10 /* sent a stop */
#define MSR_MDE 0x08
#define MSR_MDT 0x04
#define MSR_MDR 0x02
#define MSR_MAT 0x01 /* slave addr xfer done */
#define MIE_MNRE 0x40 /* nack irq en */
#define MIE_MALE 0x20 /* arblos irq en */
#define MIE_MSTE 0x10 /* stop irq en */
#define MIE_MDEE 0x08
#define MIE_MDTE 0x04
#define MIE_MDRE 0x02
#define MIE_MATE 0x01 /* address sent irq en */
#define FCR_RFRST 0x02 /* reset rx fifo */
#define FCR_TFRST 0x01 /* reset tx fifo */
#define FSR_TEND 0x04 /* last byte sent */
#define FSR_RDF 0x02 /* rx fifo trigger */
#define FSR_TDFE 0x01 /* tx fifo empty */
#define FIER_TEIE 0x04 /* tx fifo empty irq en */
#define FIER_RXIE 0x02 /* rx fifo trig irq en */
#define FIER_TXIE 0x01 /* tx fifo trig irq en */
#define FIFO_SIZE 16
struct cami2c {
void __iomem *iobase;
struct i2c_adapter adap;
/* message processing */
struct i2c_msg *msg;
#define IDF_SEND 1
#define IDF_RECV 2
#define IDF_STOP 4
int flags;
#define IDS_DONE 1
#define IDS_ARBLOST 2
#define IDS_NACK 4
int status;
struct completion xfer_done;
int irq;
struct resource *ioarea;
};
static inline void OUT32(struct cami2c *cam, int reg, unsigned long val)
{
__raw_writel(val, (unsigned long)cam->iobase + reg);
}
static inline unsigned long IN32(struct cami2c *cam, int reg)
{
return __raw_readl((unsigned long)cam->iobase + reg);
}
static irqreturn_t sh7760_i2c_irq(int irq, void *ptr)
{
struct cami2c *id = ptr;
struct i2c_msg *msg = id->msg;
char *data = msg->buf;
unsigned long msr, fsr, fier, len;
msr = IN32(id, I2CMSR);
fsr = IN32(id, I2CFSR);
/* arbitration lost */
if (msr & MSR_MAL) {
OUT32(id, I2CMCR, 0);
OUT32(id, I2CSCR, 0);
OUT32(id, I2CSAR, 0);
id->status |= IDS_DONE | IDS_ARBLOST;
goto out;
}
if (msr & MSR_MNR) {
/* NACK handling is very screwed up. After receiving a
* NAK IRQ one has to wait a bit before writing to any
* registers, or the ctl will lock up. After that delay
* do a normal i2c stop. Then wait at least 1 ms before
* attempting another transfer or ctl will stop working
*/
udelay(100); /* wait or risk ctl hang */
OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
OUT32(id, I2CFIER, 0);
OUT32(id, I2CMIER, MIE_MSTE);
OUT32(id, I2CSCR, 0);
OUT32(id, I2CSAR, 0);
id->status |= IDS_NACK;
msr &= ~MSR_MAT;
fsr = 0;
/* In some cases the MST bit is also set. */
}
/* i2c-stop was sent */
if (msr & MSR_MST) {
id->status |= IDS_DONE;
goto out;
}
/* i2c slave addr was sent; set to "normal" operation */
if (msr & MSR_MAT)
OUT32(id, I2CMCR, MCR_MIE);
fier = IN32(id, I2CFIER);
if (fsr & FSR_RDF) {
len = IN32(id, I2CRFDR);
if (msg->len <= len) {
if (id->flags & IDF_STOP) {
OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
OUT32(id, I2CFIER, 0);
/* manual says: wait >= 0.5 SCL times */
udelay(5);
/* next int should be MST */
} else {
id->status |= IDS_DONE;
/* keep the RDF bit: ctrl holds SCL low
* until the setup for the next i2c_msg
* clears this bit.
*/
fsr &= ~FSR_RDF;
}
}
while (msg->len && len) {
*data++ = IN32(id, I2CRXTX);
msg->len--;
len--;
}
if (msg->len) {
len = (msg->len >= FIFO_SIZE) ? FIFO_SIZE - 1
: msg->len - 1;
OUT32(id, I2CFCR, FCR_TFRST | ((len & 0xf) << 4));
}
} else if (id->flags & IDF_SEND) {
if ((fsr & FSR_TEND) && (msg->len < 1)) {
if (id->flags & IDF_STOP) {
OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
} else {
id->status |= IDS_DONE;
/* keep the TEND bit: ctl holds SCL low
* until the setup for the next i2c_msg
* clears this bit.
*/
fsr &= ~FSR_TEND;
}
}
if (fsr & FSR_TDFE) {
while (msg->len && (IN32(id, I2CTFDR) < FIFO_SIZE)) {
OUT32(id, I2CRXTX, *data++);
msg->len--;
}
if (msg->len < 1) {
fier &= ~FIER_TXIE;
OUT32(id, I2CFIER, fier);
} else {
len = (msg->len >= FIFO_SIZE) ? 2 : 0;
OUT32(id, I2CFCR,
FCR_RFRST | ((len & 3) << 2));
}
}
}
out:
if (id->status & IDS_DONE) {
OUT32(id, I2CMIER, 0);
OUT32(id, I2CFIER, 0);
id->msg = NULL;
complete(&id->xfer_done);
}
/* clear status flags and ctrl resumes work */
OUT32(id, I2CMSR, ~msr);
OUT32(id, I2CFSR, ~fsr);
OUT32(id, I2CSSR, 0);
return IRQ_HANDLED;
}
/* prepare and start a master receive operation */
static void sh7760_i2c_mrecv(struct cami2c *id)
{
int len;
id->flags |= IDF_RECV;
/* set the slave addr reg; otherwise rcv wont work! */
OUT32(id, I2CSAR, 0xfe);
OUT32(id, I2CMAR, (id->msg->addr << 1) | 1);
/* adjust rx fifo trigger */
if (id->msg->len >= FIFO_SIZE)
len = FIFO_SIZE -
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