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// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/qcom-geni-se.h>
#include <linux/spinlock.h>
#define SE_I2C_TX_TRANS_LEN 0x26c
#define SE_I2C_RX_TRANS_LEN 0x270
#define SE_I2C_SCL_COUNTERS 0x278
#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
#define SE_I2C_ABORT BIT(1)
/* M_CMD OP codes for I2C */
#define I2C_WRITE 0x1
#define I2C_READ 0x2
#define I2C_WRITE_READ 0x3
#define I2C_ADDR_ONLY 0x4
#define I2C_BUS_CLEAR 0x6
#define I2C_STOP_ON_BUS 0x7
/* M_CMD params for I2C */
#define PRE_CMD_DELAY BIT(0)
#define TIMESTAMP_BEFORE BIT(1)
#define STOP_STRETCH BIT(2)
#define TIMESTAMP_AFTER BIT(3)
#define POST_COMMAND_DELAY BIT(4)
#define IGNORE_ADD_NACK BIT(6)
#define READ_FINISHED_WITH_ACK BIT(7)
#define BYPASS_ADDR_PHASE BIT(8)
#define SLV_ADDR_MSK GENMASK(15, 9)
#define SLV_ADDR_SHFT 9
/* I2C SCL COUNTER fields */
#define HIGH_COUNTER_MSK GENMASK(29, 20)
#define HIGH_COUNTER_SHFT 20
#define LOW_COUNTER_MSK GENMASK(19, 10)
#define LOW_COUNTER_SHFT 10
#define CYCLE_COUNTER_MSK GENMASK(9, 0)
enum geni_i2c_err_code {
GP_IRQ0,
NACK,
GP_IRQ2,
BUS_PROTO,
ARB_LOST,
GP_IRQ5,
GENI_OVERRUN,
GENI_ILLEGAL_CMD,
GENI_ABORT_DONE,
GENI_TIMEOUT,
};
#define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
<< 5)
#define I2C_AUTO_SUSPEND_DELAY 250
#define KHZ(freq) (1000 * freq)
#define PACKING_BYTES_PW 4
#define ABORT_TIMEOUT HZ
#define XFER_TIMEOUT HZ
#define RST_TIMEOUT HZ
struct geni_i2c_dev {
struct geni_se se;
u32 tx_wm;
int irq;
int err;
struct i2c_adapter adap;
struct completion done;
struct i2c_msg *cur;
int cur_wr;
int cur_rd;
spinlock_t lock;
u32 clk_freq_out;
const struct geni_i2c_clk_fld *clk_fld;
int suspended;
};
struct geni_i2c_err_log {
int err;
const char *msg;
};
static const struct geni_i2c_err_log gi2c_log[] = {
[GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
[NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
[GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
[BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unepxected start/stop"},
[ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
[GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
[GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
[GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
[GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
[GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
};
struct geni_i2c_clk_fld {
u32 clk_freq_out;
u8 clk_div;
u8 t_high_cnt;
u8 t_low_cnt;
u8 t_cycle_cnt;
};
/*
* Hardware uses the underlying formula to calculate time periods of
* SCL clock cycle. Firmware uses some additional cycles excluded from the
* below formula and it is confirmed that the time periods are within
* specification limits.
*
* time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
* time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
* time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
* clk_freq_out = t / t_cycle
* source_clock = 19.2 MHz
*/
static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = {
{KHZ(100), 7, 10, 11, 26},
{KHZ(400), 2, 5, 12, 24},
{KHZ(1000), 1, 3, 9, 18},
};
static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
{
int i;
const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map;
for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) {
if (itr->clk_freq_out == gi2c->clk_freq_out) {
gi2c->clk_fld = itr;
return 0;
}
}
return -EINVAL;
}
static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
{
const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
u32 val;
writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
val |= itr->t_cycle_cnt;
writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
}
static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
{
u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
u32 rx_st, tx_st;
if (dma) {
rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
} else {
rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
}
dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
dma, tx_st, rx_st, m_stat);
dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
m_cmd, geni_s, geni_ios);
}
static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
{
if (!gi2c->err)
gi2c->err = gi2c_log[err].err;
if (gi2c->cur)
dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
if (err != NACK && err != GENI_ABORT_DONE) {
dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
geni_i2c_err_misc(gi2c);
}
}
static irqreturn_t geni_i2c_irq(int irq, void *dev)
{
struct geni_i2c_dev *gi2c = dev;
void __iomem *base = gi2c->se.base;
int j, p;
u32 m_stat;
u32 rx_st;
u32 dm_tx_st
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