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|
/*
i2c Support for Apple SMU Controller
Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp.
<benh@kernel.crashing.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/of_irq.h>
#include <asm/prom.h>
#include <asm/pmac_low_i2c.h>
MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
MODULE_DESCRIPTION("I2C driver for Apple PowerMac");
MODULE_LICENSE("GPL");
/*
* SMBUS-type transfer entrypoint
*/
static s32 i2c_powermac_smbus_xfer( struct i2c_adapter* adap,
u16 addr,
unsigned short flags,
char read_write,
u8 command,
int size,
union i2c_smbus_data* data)
{
struct pmac_i2c_bus *bus = i2c_get_adapdata(adap);
int rc = 0;
int read = (read_write == I2C_SMBUS_READ);
int addrdir = (addr << 1) | read;
int mode, subsize, len;
u32 subaddr;
u8 *buf;
u8 local[2];
if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE) {
mode = pmac_i2c_mode_std;
subsize = 0;
subaddr = 0;
} else {
mode = read ? pmac_i2c_mode_combined : pmac_i2c_mode_stdsub;
subsize = 1;
subaddr = command;
}
switch (size) {
case I2C_SMBUS_QUICK:
buf = NULL;
len = 0;
break;
case I2C_SMBUS_BYTE:
case I2C_SMBUS_BYTE_DATA:
buf = &data->byte;
len = 1;
break;
case I2C_SMBUS_WORD_DATA:
if (!read) {
local[0] = data->word & 0xff;
local[1] = (data->word >> 8) & 0xff;
}
buf = local;
len = 2;
break;
/* Note that these are broken vs. the expected smbus API where
* on reads, the length is actually returned from the function,
* but I think the current API makes no sense and I don't want
* any driver that I haven't verified for correctness to go
* anywhere near a pmac i2c bus anyway ...
*
* I'm also not completely sure what kind of phases to do between
* the actual command and the data (what I am _supposed_ to do that
* is). For now, I assume writes are a single stream and reads have
* a repeat start/addr phase (but not stop in between)
*/
case I2C_SMBUS_BLOCK_DATA:
buf = data->block;
len = data->block[0] + 1;
break;
case I2C_SMBUS_I2C_BLOCK_DATA:
buf = &data->block[1];
len = data->block[0];
break;
default:
return -EINVAL;
}
rc = pmac_i2c_open(bus, 0);
if (rc) {
dev_err(&adap->dev, "Failed to open I2C, err %d\n", rc);
return rc;
}
rc = pmac_i2c_setmode(bus, mode);
if (rc) {
dev_err(&adap->dev, "Failed to set I2C mode %d, err %d\n",
mode, rc);
goto bail;
}
rc = pmac_i2c_xfer(bus, addrdir, subsize, subaddr, buf, len);
if (rc) {
if (rc == -ENXIO)
dev_dbg(&adap->dev,
"I2C transfer at 0x%02x failed, size %d, "
"err %d\n", addrdir >> 1, size, rc);
else
dev_err(&adap->dev,
"I2C transfer at 0x%02x failed, size %d, "
"err %d\n", addrdir >> 1, size, rc);
goto bail;
}
if (size == I2C_SMBUS_WORD_DATA && read) {
data->word = ((u16)local[1]) << 8;
data->word |= local[0];
}
bail:
pmac_i2c_close(bus);
return rc;
}
/*
* Generic i2c master transfer entrypoint. This driver only support single
* messages (for "lame i2c" transfers). Anything else should use the smbus
* entry point
*/
static int i2c_powermac_master_xfer( struct i2c_adapter *adap,
struct i2c_msg *msgs,
int num)
{
struct pmac_i2c_bus *bus = i2c_get_adapdata(adap);
int rc = 0;
int addrdir;
if (msgs->flags & I2C_M_TEN)
return -EINVAL;
addrdir = i2c_8bit_addr_from_msg(msgs);
rc = pmac_i2c_open(bus, 0);
if (rc) {
dev_err(&adap->dev, "Failed to open I2C, err %d\n", rc);
return rc;
}
rc = pmac_i2c_setmode(bus, pmac_i2c_mode_std);
if (rc) {
dev_err(&adap->dev, "Failed to set I2C mode %d, err %d\n",
pmac_i2c_mode_std, rc);
goto bail;
}
rc = pmac_i2c_xfer(bus, addrdir, 0, 0, msgs->buf, msgs->len);
if (rc < 0) {
if (rc == -ENXIO)
dev_dbg(&adap->dev, "I2C %s 0x%02x failed, err %d\n",
addrdir & 1 ? "read from" : "write to",
addrdir >> 1, rc);
else
dev_err(&adap->dev, "I2C %s 0x%02x failed, err %d\n",
addrdir & 1 ? "read from" : "write to",
addrdir >> 1, rc);
}
bail:
pmac_i2c_close(bus);
return rc < 0 ? rc : 1;
}
static u32 i2c_powermac_func(struct i2c_adapter * adapter)
{
return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_I2C;
}
/* For now, we only handle smbus */
static const struct i2c_algorithm i2c_powermac_algorithm = {
.smbus_xfer = i2c_powermac_smbus_xfer,
.master_xfer = i2c_powermac_master_xfer,
.functionality = i2c_powermac_func,
};
static const struct i2c_adapter_quirks i2c_powermac_quirks = {
.max_num_msgs = 1,
};
static int i2c_powermac_remove(struct platform_device *dev)
{
struct i2c_adapter *adapter = platform_get_drvdata(dev);
i2c_del_adapter(adapter);
memset(adapter, 0, sizeof(*adapter));
return 0;
}
static u32 i2c_powermac_get_addr(struct i2c_adapter *adap,
struct pmac_i2c_bus *bus,
struct device_node *node)
{
const __be32 *prop;
int len;
/* First check for valid "reg" */
prop = of_get_property(node, "reg", &len);
if (prop && (len >= sizeof(int)))
return (be32_to_cpup(prop) & 0xff) >> 1;
/* Then check old-style "i2c-address" */
prop = of_get_property(node, "i2c-address", &len);
if (prop && (len >= sizeof(int)))
return (be32_to_cpup(prop) & 0xff) >> 1;
/* Now handle some devices with missing "reg" properties */
if (of_node_name_eq(node, "cereal"))
return 0x60;
else if (of_node_name_eq(node, "deq"))
return 0x34;
dev_warn(&adap->dev, "No i2c address for %pOF\n", node);
return 0xffffffff;
}
static void i2c_powermac_create_one(struct i2c_adapter *adap,
const char *type,
u32 addr)
{
struct i2c_board_info info
|