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// SPDX-License-Identifier: GPL-2.0+
/*
* This is i.MX low power i2c controller driver.
*
* Copyright 2016 Freescale Semiconductor, Inc.
*/
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/sched.h>
#include <linux/slab.h>
#define DRIVER_NAME "imx-lpi2c"
#define LPI2C_PARAM 0x04 /* i2c RX/TX FIFO size */
#define LPI2C_MCR 0x10 /* i2c contrl register */
#define LPI2C_MSR 0x14 /* i2c status register */
#define LPI2C_MIER 0x18 /* i2c interrupt enable */
#define LPI2C_MCFGR0 0x20 /* i2c master configuration */
#define LPI2C_MCFGR1 0x24 /* i2c master configuration */
#define LPI2C_MCFGR2 0x28 /* i2c master configuration */
#define LPI2C_MCFGR3 0x2C /* i2c master configuration */
#define LPI2C_MCCR0 0x48 /* i2c master clk configuration */
#define LPI2C_MCCR1 0x50 /* i2c master clk configuration */
#define LPI2C_MFCR 0x58 /* i2c master FIFO control */
#define LPI2C_MFSR 0x5C /* i2c master FIFO status */
#define LPI2C_MTDR 0x60 /* i2c master TX data register */
#define LPI2C_MRDR 0x70 /* i2c master RX data register */
/* i2c command */
#define TRAN_DATA 0X00
#define RECV_DATA 0X01
#define GEN_STOP 0X02
#define RECV_DISCARD 0X03
#define GEN_START 0X04
#define START_NACK 0X05
#define START_HIGH 0X06
#define START_HIGH_NACK 0X07
#define MCR_MEN BIT(0)
#define MCR_RST BIT(1)
#define MCR_DOZEN BIT(2)
#define MCR_DBGEN BIT(3)
#define MCR_RTF BIT(8)
#define MCR_RRF BIT(9)
#define MSR_TDF BIT(0)
#define MSR_RDF BIT(1)
#define MSR_SDF BIT(9)
#define MSR_NDF BIT(10)
#define MSR_ALF BIT(11)
#define MSR_MBF BIT(24)
#define MSR_BBF BIT(25)
#define MIER_TDIE BIT(0)
#define MIER_RDIE BIT(1)
#define MIER_SDIE BIT(9)
#define MIER_NDIE BIT(10)
#define MCFGR1_AUTOSTOP BIT(8)
#define MCFGR1_IGNACK BIT(9)
#define MRDR_RXEMPTY BIT(14)
#define I2C_CLK_RATIO 2
#define CHUNK_DATA 256
#define LPI2C_DEFAULT_RATE 100000
#define STARDARD_MAX_BITRATE 400000
#define FAST_MAX_BITRATE 1000000
#define FAST_PLUS_MAX_BITRATE 3400000
#define HIGHSPEED_MAX_BITRATE 5000000
#define I2C_PM_TIMEOUT 10 /* ms */
enum lpi2c_imx_mode {
STANDARD, /* 100+Kbps */
FAST, /* 400+Kbps */
FAST_PLUS, /* 1.0+Mbps */
HS, /* 3.4+Mbps */
ULTRA_FAST, /* 5.0+Mbps */
};
enum lpi2c_imx_pincfg {
TWO_PIN_OD,
TWO_PIN_OO,
TWO_PIN_PP,
FOUR_PIN_PP,
};
struct lpi2c_imx_struct {
struct i2c_adapter adapter;
struct clk *clk;
void __iomem *base;
__u8 *rx_buf;
__u8 *tx_buf;
struct completion complete;
unsigned int msglen;
unsigned int delivered;
unsigned int block_data;
unsigned int bitrate;
unsigned int txfifosize;
unsigned int rxfifosize;
enum lpi2c_imx_mode mode;
};
static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx,
unsigned int enable)
{
writel(enable, lpi2c_imx->base + LPI2C_MIER);
}
static int lpi2c_imx_bus_busy(struct lpi2c_imx_struct *lpi2c_imx)
{
unsigned long orig_jiffies = jiffies;
unsigned int temp;
while (1) {
temp = readl(lpi2c_imx->base + LPI2C_MSR);
/* check for arbitration lost, clear if set */
if (temp & MSR_ALF) {
writel(temp, lpi2c_imx->base + LPI2C_MSR);
return -EAGAIN;
}
if (temp & (MSR_BBF | MSR_MBF))
break;
if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
dev_dbg(&lpi2c_imx->adapter.dev, "bus not work\n");
return -ETIMEDOUT;
}
schedule();
}
return 0;
}
static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx)
{
unsigned int bitrate = lpi2c_imx->bitrate;
enum lpi2c_imx_mode mode;
if (bitrate < STARDARD_MAX_BITRATE)
mode = STANDARD;
else if (bitrate < FAST_MAX_BITRATE)
mode = FAST;
else if (bitrate < FAST_PLUS_MAX_BITRATE)
mode = FAST_PLUS;
else if (bitrate < HIGHSPEED_MAX_BITRATE)
mode = HS;
else
mode = ULTRA_FAST;
lpi2c_imx->mode = mode;
}
static int lpi2c_imx_start(struct lpi2c_imx_struct *lpi2c_imx,
struct i2c_msg *msgs)
{
unsigned int temp;
temp = readl(lpi2c_imx->base + LPI2C_MCR);
temp |= MCR_RRF | MCR_RTF;
writel(temp, lpi2c_imx->base + LPI2C_MCR);
writel(0x7f00, lpi2c_imx->base + LPI2C_MSR);
temp = i2c_8bit_addr_from_msg(msgs) | (GEN_START << 8);
writel(temp, lpi2c_imx->base + LPI2C_MTDR);
return lpi2c_imx_bus_busy(lpi2c_imx);
}
static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx)
{
unsigned long orig_jiffies = jiffies;
unsigned int temp;
writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR);
do {
temp = readl(lpi2c_imx->base + LPI2C_MSR);
if (temp & MSR_SDF)
break;
if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
dev_dbg(&lpi2c_imx->adapter.dev, "stop timeout\n");
break;
}
schedule();
} while (1);
}
/* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */
static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx)
{
u8 prescale, filt, sethold, clkhi, clklo, datavd;
unsigned int clk_rate, clk_cycle;
enum lpi2c_imx_pincfg pincfg;
unsigned int temp;
lpi2c_imx_set_mode(lpi2c_imx);
clk_rate = clk_get_rate(lpi2c_imx->clk);
if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST)
filt = 0;
else
filt = 2;
for (prescale = 0; prescale <= 7; prescale++) {
clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate)
- 3 - (filt >> 1);
clkhi = (clk_cycle + I2C_CLK_RATIO) / (I2C_CLK_RATIO + 1);
clklo = clk_cycle - clkhi;
if (clklo < 64)
break;
}
if (prescale > 7)
return -EINVAL;
/* set MCFGR1: PINCFG, PRESCALE, IGNACK */
if (lpi2c_imx->mode == ULTRA_FAST)
pincfg = TWO_PIN_OO;
else
pincfg = TWO_PIN_OD;
temp = prescale | pincfg << 24;
if (lpi2c_imx->mode == ULTRA_FAST)
temp |= MCFGR1_IGNACK;
writel(temp, lpi2c_imx->base +
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