/*
* I2C adapter for the IMG Serial Control Bus (SCB) IP block.
*
* Copyright (C) 2009, 2010, 2012, 2014 Imagination Technologies Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* There are three ways that this I2C controller can be driven:
*
* - Raw control of the SDA and SCK signals.
*
* This corresponds to MODE_RAW, which takes control of the signals
* directly for a certain number of clock cycles (the INT_TIMING
* interrupt can be used for timing).
*
* - Atomic commands. A low level I2C symbol (such as generate
* start/stop/ack/nack bit, generate byte, receive byte, and receive
* ACK) is given to the hardware, with detection of completion by bits
* in the LINESTAT register.
*
* This mode of operation is used by MODE_ATOMIC, which uses an I2C
* state machine in the interrupt handler to compose/react to I2C
* transactions using atomic mode commands, and also by MODE_SEQUENCE,
* which emits a simple fixed sequence of atomic mode commands.
*
* Due to software control, the use of atomic commands usually results
* in suboptimal use of the bus, with gaps between the I2C symbols while
* the driver decides what to do next.
*
* - Automatic mode. A bus address, and whether to read/write is
* specified, and the hardware takes care of the I2C state machine,
* using a FIFO to send/receive bytes of data to an I2C slave. The
* driver just has to keep the FIFO drained or filled in response to the
* appropriate FIFO interrupts.
*
* This corresponds to MODE_AUTOMATIC, which manages the FIFOs and deals
* with control of repeated start bits between I2C messages.
*
* Use of automatic mode and the FIFO can make much more efficient use
* of the bus compared to individual atomic commands, with potentially
* no wasted time between I2C symbols or I2C messages.
*
* In most cases MODE_AUTOMATIC is used, however if any of the messages in
* a transaction are zero byte writes (e.g. used by i2cdetect for probing
* the bus), MODE_ATOMIC must be used since automatic mode is normally
* started by the writing of data into the FIFO.
*
* The other modes are used in specific circumstances where MODE_ATOMIC and
* MODE_AUTOMATIC aren't appropriate. MODE_RAW is used to implement a bus
* recovery routine. MODE_SEQUENCE is used to reset the bus and make sure
* it is in a sane state.
*
* Notice that the driver implements a timer-based timeout mechanism.
* The reason for this mechanism is to reduce the number of interrupts
* received in automatic mode.
*
* The driver would get a slave event and transaction done interrupts for
* each atomic mode command that gets completed. However, these events are
* not needed in automatic mode, becase those atomic mode commands are
* managed automatically by the hardware.
*
* In practice, normal I2C transactions will be complete well before you
* get the timer interrupt, as the timer is re-scheduled during FIFO
* maintenance and disabled after the transaction is complete.
*
* In this way normal automatic mode operation isn't impacted by
* unnecessary interrupts, but the exceptional abort condition can still be
* detected (with a slight delay).
*/
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/timer.h>
/* Register offsets */
#define SCB_STATUS_REG 0x00
#define SCB_OVERRIDE_REG 0x04
#define SCB_READ_ADDR_REG 0x08
#define SCB_READ_COUNT_REG 0x0c
#define SCB_WRITE_ADDR_REG 0x10
#define SCB_READ_DATA_REG 0x14
#define SCB_WRITE_DATA_REG 0x18
#define SCB_FIFO_STATUS_REG 0x1c
#define SCB_CONTROL_SOFT_RESET 0x1f
#define SCB_CLK_SET_REG 0x3c
#define SCB_INT_STATUS_REG 0x40
#define SCB_INT_CLEAR_REG 0x44