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/**
* i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
*
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/spinlock.h>
/*
* HSI2C controller from Samsung supports 2 modes of operation
* 1. Auto mode: Where in master automatically controls the whole transaction
* 2. Manual mode: Software controls the transaction by issuing commands
* START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
*
* Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
*
* Special bits are available for both modes of operation to set commands
* and for checking transfer status
*/
/* Register Map */
#define HSI2C_CTL 0x00
#define HSI2C_FIFO_CTL 0x04
#define HSI2C_TRAILIG_CTL 0x08
#define HSI2C_CLK_CTL 0x0C
#define HSI2C_CLK_SLOT 0x10
#define HSI2C_INT_ENABLE 0x20
#define HSI2C_INT_STATUS 0x24
#define HSI2C_ERR_STATUS 0x2C
#define HSI2C_FIFO_STATUS 0x30
#define HSI2C_TX_DATA 0x34
#define HSI2C_RX_DATA 0x38
#define HSI2C_CONF 0x40
#define HSI2C_AUTO_CONF 0x44
#define HSI2C_TIMEOUT 0x48
#define HSI2C_MANUAL_CMD 0x4C
#define HSI2C_TRANS_STATUS 0x50
#define HSI2C_TIMING_HS1 0x54
#define HSI2C_TIMING_HS2 0x58
#define HSI2C_TIMING_HS3 0x5C
#define HSI2C_TIMING_FS1 0x60
#define HSI2C_TIMING_FS2 0x64
#define HSI2C_TIMING_FS3 0x68
#define HSI2C_TIMING_SLA 0x6C
#define HSI2C_ADDR 0x70
/* I2C_CTL Register bits */
#define HSI2C_FUNC_MODE_I2C (1u << 0)
#define HSI2C_MASTER (1u << 3)
#define HSI2C_RXCHON (1u << 6)
#define HSI2C_TXCHON (1u << 7)
#define HSI2C_SW_RST (1u << 31)
/* I2C_FIFO_CTL Register bits */
#define HSI2C_RXFIFO_EN (1u << 0)
#define HSI2C_TXFIFO_EN (1u << 1)
#define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
#define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
/* I2C_TRAILING_CTL Register bits */
#define HSI2C_TRAILING_COUNT (0xf)
/* I2C_INT_EN Register bits */
#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
#define HSI2C_INT_TRAILING_EN (1u << 6)
/* I2C_INT_STAT Register bits */
#define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)
#define HSI2C_INT_RX_ALMOSTFULL (1u << 1)
#define HSI2C_INT_TX_UNDERRUN (1u << 2)
#define HSI2C_INT_TX_OVERRUN (1u << 3)
#define HSI2C_INT_RX_UNDERRUN (1u << 4)
#define HSI2C_INT_RX_OVERRUN (1u << 5)
#define HSI2C_INT_TRAILING (1u << 6)
#define HSI2C_INT_I2C (1u << 9)
#define HSI2C_INT_TRANS_DONE (1u << 7)
#define HSI2C_INT_TRANS_ABORT (1u << 8)
#define HSI2C_INT_NO_DEV_ACK (1u << 9)
#define HSI2C_INT_NO_DEV (1u << 10)
#define HSI2C_INT_TIMEOUT (1u << 11)
#define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \
HSI2C_INT_TRANS_ABORT | \
HSI2C_INT_NO_DEV_ACK | \
HSI2C_INT_NO_DEV | \
HSI2C_INT_TIMEOUT)
/* I2C_FIFO_STAT Register bits */
#define HSI2C_RX_FIFO_EMPTY (1u << 24)
#define HSI2C_RX_FIFO_FULL (1u << 23)
#define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)
#define HSI2C_TX_FIFO_EMPTY (1u << 8)
#define HSI2C_TX_FIFO_FULL (1u << 7)
#define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)
/* I2C_CONF Register bits */
#define HSI2C_AUTO_MODE (1u << 31)
#define HSI2C_10BIT_ADDR_MODE (1u << 30)
#define HSI2C_HS_MODE (1u << 29)
/* I2C_AUTO_CONF Register bits */
#define HSI2C_READ_WRITE (1u << 16)
#define HSI2C_STOP_AFTER_TRANS (1u << 17)
#define HSI2C_MASTER_RUN (1u << 31)
/* I2C_TIMEOUT Register bits */
#define HSI2C_TIMEOUT_EN (1u << 31)
#define HSI2C_TIMEOUT_MASK 0xff
/* I2C_TRANS_STATUS register bits */
#define HSI2C_MASTER_BUSY (1u << 17)
#define HSI2C_SLAVE_BUSY (1u << 16)
/* I2C_TRANS_STATUS register bits for Exynos5 variant */
#define HSI2C_TIMEOUT_AUTO (1u << 4)
#define HSI2C_NO_DEV (1u << 3)
#define HSI2C_NO_DEV_ACK (1u << 2)
#define HSI2C_TRANS_ABORT (1u << 1)
#define HSI2C_TRANS_DONE (1u << 0)
/* I2C_TRANS_STATUS register bits for Exynos7 variant */
#define HSI2C_MASTER_ST_MASK 0xf
#define HSI2C_MASTER_ST_IDLE 0x0
#define HSI2C_MASTER_ST_START 0x1
#define HSI2C_MASTER_ST_RESTART 0x2
#define HSI2C_MASTER_ST_STOP 0x3
#define HSI2C_MASTER_ST_MASTER_ID 0x4
#define HSI2C_MASTER_ST_ADDR0 0x5
#define HSI2C_MASTER_ST_ADDR1 0x6
#define HSI2C_MASTER_ST_ADDR2 0x7
#define HSI2C_MASTER_ST_ADDR_SR 0x8
#define HSI2C_MASTER_ST_READ 0x9
#define HSI2C_MASTER_ST_WRITE 0xa
#define HSI2C_MASTER_ST_NO_ACK 0xb
#define HSI2C_MASTER_ST_LOSE 0xc
#define HSI2C_MASTER_ST_WAIT 0xd
#define HSI2C_MASTER_ST_WAIT_CMD 0xe
/* I2C_ADDR register bits */
#define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
#define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
#define MASTER_ID(x) ((x & 0x7) + 0x08)
/*
* Controller operating frequency, timing values for operation
* are calculated against this frequency
*/
#define HSI2C_HS_TX_CLOCK 1000000
#define HSI2C_FS_TX_CLOCK 100000
#define HSI2C_HIGH_SPD 1
#define HSI2C_FAST_SPD 0
#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
#define HSI2C_EXYNOS7 BIT(0)
struct exynos5_i2c {
struct i2c_adapter adap;
unsigned int suspended:1;
struct i2c_msg *msg;
struct completion msg_complete;
unsigned int msg_ptr;
unsigned int irq;
void __iomem *regs;
struct clk *clk;
struct device *dev;
int state;
spinlock_t lock; /* IRQ synchronization */
/*
* Since the TRANS_DONE bit is cleared on read, and we may read it
* either during an IRQ or after a transaction, keep track of its
* state here.
*/
int trans_done;
/* Controller operating frequency */
unsigned int fs_clock;
unsigned int hs_clock;
/*
* HSI2C Controller can operate in
* 1. High speed upto 3.4Mbps
* 2. Fast speed upto 1Mbps
*/
int speed_mode;
/* Version of HS-I2C Hardware */
struct exynos_hsi2c_variant *variant;
};
/**
* struct exynos_hsi2c_variant - platform specific HSI2C driver data
* @fifo_depth: the fifo depth supported by the HSI2C module
*
* Specifies platform specific configuration of HSI2C module.
* Note: A structure for driver specific platform data is used for future
* expansion of its usage.
*/
struct exynos_hsi2c_variant {
unsigned int fifo_depth;
unsigned int hw;
};
static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
.fifo_depth = 64,
};
static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
.fifo_depth = 16,
};
static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
.fifo_depth = 16,
.hw = HSI2C_EXYNOS7,
};
static const struct of_device_id exynos5_i2c_match[] = {
{
.compatible = "samsung,exynos5-hsi2c",
.data = &exynos5250_hsi2c_data
}, {
.compatible = "samsung,exynos5250-hsi2c",
.data = &exynos5250_hsi2c_data
}, {
.compatible = "samsung,exynos5260-hsi2c",
.data = &exynos5260_hsi2c_data
}, {
.compatible = "samsung,exynos7-hsi2c",
.data = &exynos7_hsi2c_data
}, {},
};
MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
static inline struct exynos_hsi2c_variant *exynos5_i2c_get_variant
(struct platform_device *pdev)
{
const struct of_device_id *match;
match = of_match_node(exynos5_i2c_match, pdev->dev.of_node);
return (struct exynos_hsi2c_variant *)match->data;
}
static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
{
writel(readl(i2c->regs + HSI2C_INT_STATUS),
i2c->regs + HSI2C_INT_STATUS);
}
/*
* exynos5_i2c_set_timing: updates the registers with appropriate
* timing values calculated
*
* Returns 0 on success, -EINVAL if the cycle length cannot
* be calculated.
*/
static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)
{
u32 i2c_timing_s1;
u32 i2c_timing_s2;
u32 i2c_timing_s3;
u32 i2c_timing_sla;
unsigned int t_start_su, t_start_hd;
unsigned int t_stop_su;
unsigned int t_data_su, t_data_hd;
unsigned int t_scl_l, t_scl_h;
unsigned int t_sr_release;
unsigned int t_ftl_cycle;
unsigned int clkin =
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