1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
|
// SPDX-License-Identifier: GPL-2.0
/*
* I2C driver for the Renesas EMEV2 SoC
*
* Copyright (C) 2015 Wolfram Sang <wsa@sang-engineering.com>
* Copyright 2013 Codethink Ltd.
* Copyright 2010-2015 Renesas Electronics Corporation
*/
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
/* I2C Registers */
#define I2C_OFS_IICACT0 0x00 /* start */
#define I2C_OFS_IIC0 0x04 /* shift */
#define I2C_OFS_IICC0 0x08 /* control */
#define I2C_OFS_SVA0 0x0c /* slave address */
#define I2C_OFS_IICCL0 0x10 /* clock select */
#define I2C_OFS_IICX0 0x14 /* extension */
#define I2C_OFS_IICS0 0x18 /* status */
#define I2C_OFS_IICSE0 0x1c /* status For emulation */
#define I2C_OFS_IICF0 0x20 /* IIC flag */
/* I2C IICACT0 Masks */
#define I2C_BIT_IICE0 0x0001
/* I2C IICC0 Masks */
#define I2C_BIT_LREL0 0x0040
#define I2C_BIT_WREL0 0x0020
#define I2C_BIT_SPIE0 0x0010
#define I2C_BIT_WTIM0 0x0008
#define I2C_BIT_ACKE0 0x0004
#define I2C_BIT_STT0 0x0002
#define I2C_BIT_SPT0 0x0001
/* I2C IICCL0 Masks */
#define I2C_BIT_SMC0 0x0008
#define I2C_BIT_DFC0 0x0004
/* I2C IICSE0 Masks */
#define I2C_BIT_MSTS0 0x0080
#define I2C_BIT_ALD0 0x0040
#define I2C_BIT_EXC0 0x0020
#define I2C_BIT_COI0 0x0010
#define I2C_BIT_TRC0 0x0008
#define I2C_BIT_ACKD0 0x0004
#define I2C_BIT_STD0 0x0002
#define I2C_BIT_SPD0 0x0001
/* I2C IICF0 Masks */
#define I2C_BIT_STCF 0x0080
#define I2C_BIT_IICBSY 0x0040
#define I2C_BIT_STCEN 0x0002
#define I2C_BIT_IICRSV 0x0001
struct em_i2c_device {
void __iomem *base;
struct i2c_adapter adap;
struct completion msg_done;
struct clk *sclk;
struct i2c_client *slave;
};
static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg)
{
writeb((readb(priv->base + reg) & ~clear) | set, priv->base + reg);
}
static int em_i2c_wait_for_event(struct em_i2c_device *priv)
{
unsigned long time_left;
int status;
reinit_completion(&priv->msg_done);
time_left = wait_for_completion_timeout(&priv->msg_done, priv->adap.timeout);
if (!time_left)
return -ETIMEDOUT;
status = readb(priv->base + I2C_OFS_IICSE0);
return status & I2C_BIT_ALD0 ? -EAGAIN : status;
}
static void em_i2c_stop(struct em_i2c_device *priv)
{
/* Send Stop condition */
em_clear_set_bit(priv, 0, I2C_BIT_SPT0 | I2C_BIT_SPIE0, I2C_OFS_IICC0);
/* Wait for stop condition */
em_i2c_wait_for_event(priv);
}
static void em_i2c_reset(struct i2c_adapter *adap)
{
struct em_i2c_device *priv = i2c_get_adapdata(adap);
int retr;
/* If I2C active */
if (readb(priv->base + I2C_OFS_IICACT0) & I2C_BIT_IICE0) {
/* Disable I2C operation */
writeb(0, priv->base + I2C_OFS_IICACT0);
retr = 1000;
while (readb(priv->base + I2C_OFS_IICACT0) == 1 && retr)
retr--;
WARN_ON(retr == 0);
}
/* Transfer mode set */
writeb(I2C_BIT_DFC0, priv->base + I2C_OFS_IICCL0);
/* Can Issue start without detecting a stop, Reservation disabled. */
writeb(I2C_BIT_STCEN | I2C_BIT_IICRSV, priv->base + I2C_OFS_IICF0);
/* I2C enable, 9 bit interrupt mode */
writeb(I2C_BIT_WTIM0, priv->base + I2C_OFS_IICC0);
/* Enable I2C operation */
writeb(I2C_BIT_IICE0, priv->base + I2C_OFS_IICACT0);
retr = 1000;
while (readb(priv->base + I2C_OFS_IICACT0) == 0 && retr)
retr--;
WARN_ON(retr == 0);
}
static int __em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
int stop)
{
struct em_i2c_device *priv = i2c_get_adapdata(adap);
int count, status, read = !!(msg->flags & I2C_M_RD);
/* Send start condition */
em_clear_set_bit(priv, 0, I2C_BIT_ACKE0 | I2C_BIT_WTIM0, I2C_OFS_IICC0);
em_clear_set_bit(priv, 0, I2C_BIT_STT0, I2C_OFS_IICC0);
/* Send slave address and R/W type */
writeb(i2c_8bit_addr_from_msg(msg), priv->base + I2C_OFS_IIC0);
/* Wait for transaction */
status = em_i2c_wait_for_event(priv);
if (status < 0)
goto out_reset;
/* Received NACK (result of setting slave address and R/W) */
if (!(status & I2C_BIT_ACKD0)) {
em_i2c_stop(priv);
goto out;
}
/* Extra setup for read transactions */
if (read) {
/* 8 bit interrupt mode */
em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, I2C_OFS_IICC0);
em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, I2C_OFS_IICC0);
/* Wait for transaction */
status = em_i2c_wait_for_event(priv);
if (status < 0)
goto out_reset;
}
/* Send / receive data */
for (count = 0; count < msg->len; count++) {
if (read) { /* Read transaction */
msg->buf[count] = readb(priv->base + I2C_OFS_IIC0);
em_clear_set_bit(priv, 0, I2C_BIT_WREL0, I2C_OFS_IICC0);
} else { /* Write transaction */
/* Received NACK */
if (!(status & I2C_BIT_ACKD0)) {
em_i2c_stop(priv);
goto out;
}
/* Write data */
writeb(msg->buf[count], priv->base + I2C_OFS_IIC0);
}
/* Wait for R/W transaction */
status = em_i2c_wait_for_event(priv);
if (status < 0)
goto out_reset;
}
if (stop)
em_i2c_stop(priv);
return count;
out_reset:
em_i2c_reset(adap);
out:
return status < 0 ? status : -ENXIO;
}
static int em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
int num)
{
struct em_i2c_device *priv = i2c_get_adapdata(adap);
int ret, i;
if (readb(priv->base + I2C_OFS_IICF0) & I2C_BIT_IICBSY)
return -EAGAIN;
for (i = 0; i < num; i++) {
ret = __em_i2c_xfer(adap, &msgs[i], (i == (num - 1)));
if (ret < 0)
return ret;
}
/* I2C transfer completed */
return num;
}
static bool em_i2c_slave_irq(struct em_i2c_device *priv)
{
u8 status, value;
enum i2c_slave_event event;
int ret;
if (!priv->slave)
return false;
status = readb(priv->base + I2C_OFS_IICSE0);
/* Extension code, do not participate */
if (status & I2C_BIT_EXC0) {
em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
return true;
}
/* Stop detected, we don't know if it's for slave or master */
if (status & I2C_BIT_SPD0) {
/* Notify slave device */
i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
/* Pretend we did not handle the interrupt */
return false;
}
/* Only handle interrupts addressed to us */
if (!(status & I2C_BIT_COI0))
return false;
/* Enable stop interrupts */
em_clear_set_bit(priv, 0, I2C_BIT_SPIE0, I2C_OFS_IICC0);
/* Transmission or Reception */
if (status & I2C_BIT_TRC0) {
if (status & I2C_BIT_ACKD0) {
/* 9 bit interrupt mode */
em_clear_set_bit(priv, 0, I2C_BIT_WTIM0, I2C_OFS_IICC0);
/* Send data */
event = status & I2C_BIT_STD0 ?
I2C_SLAVE_READ_REQUESTED :
I2C_SLAVE_READ_PROCESSED;
i2c_slave_event(priv->slave, event, &value);
writeb(value, priv->base + I2C_OFS_IIC0);
} else {
/* NACK, stop transmitting */
em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
}
} else {
/* 8 bit interrupt mode */
em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0,
I2C_OFS_IICC0);
em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0,
I2C_OFS_IICC0);
if (status & I2C_BIT_STD0
|