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/*
* Copyright (C) 2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/version.h>
#define N_DATA_REGS 8
/*
* PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
* size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per
* data register whereas STB SoCs use 4 byte per data register transfer,
* account for this difference in total count per transaction and mask to
* use.
*/
#define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))
#define BSC_CNT_REG1_SHIFT 0
/* BSC CTL register field definitions */
#define BSC_CTL_REG_DTF_MASK 0x00000003
#define BSC_CTL_REG_SCL_SEL_MASK 0x00000030
#define BSC_CTL_REG_SCL_SEL_SHIFT 4
#define BSC_CTL_REG_INT_EN_MASK 0x00000040
#define BSC_CTL_REG_INT_EN_SHIFT 6
#define BSC_CTL_REG_DIV_CLK_MASK 0x00000080
/* BSC_IIC_ENABLE r/w enable and interrupt field definitions */
#define BSC_IIC_EN_RESTART_MASK 0x00000040
#define BSC_IIC_EN_NOSTART_MASK 0x00000020
#define BSC_IIC_EN_NOSTOP_MASK 0x00000010
#define BSC_IIC_EN_NOACK_MASK 0x00000004
#define BSC_IIC_EN_INTRP_MASK 0x00000002
#define BSC_IIC_EN_ENABLE_MASK 0x00000001
/* BSC_CTLHI control register field definitions */
#define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080
#define BSC_CTLHI_REG_DATAREG_SIZE_MASK 0x00000040
#define BSC_CTLHI_REG_IGNORE_ACK_MASK 0x00000002
#define BSC_CTLHI_REG_WAIT_DIS_MASK 0x00000001
#define I2C_TIMEOUT 100 /* msecs */
/* Condition mask used for non combined transfer */
#define COND_RESTART BSC_IIC_EN_RESTART_MASK
#define COND_NOSTART BSC_IIC_EN_NOSTART_MASK
#define COND_NOSTOP BSC_IIC_EN_NOSTOP_MASK
#define COND_START_STOP (COND_RESTART | COND_NOSTART | COND_NOSTOP)
/* BSC data transfer direction */
#define DTF_WR_MASK 0x00000000
#define DTF_RD_MASK 0x00000001
/* BSC data transfer direction combined format */
#define DTF_RD_WR_MASK 0x00000002
#define DTF_WR_RD_MASK 0x00000003
#define INT_ENABLE true
#define INT_DISABLE false
/* BSC block register map structure to cache fields to be written */
struct bsc_regs {
u32 chip_address; /* slave address */
u32 data_in[N_DATA_REGS]; /* tx data buffer*/
u32 cnt_reg; /* rx/tx data length */
u32 ctl_reg; /* control register */
u32 iic_enable; /* xfer enable and status */
u32 data_out[N_DATA_REGS]; /* rx data buffer */
u32 ctlhi_reg; /* more control fields */
u32 scl_param; /* reserved */
};
struct bsc_clk_param {
u32 hz;
u32 scl_mask;
u32 div_mask;
};
enum bsc_xfer_cmd {
CMD_WR,
CMD_RD,
CMD_WR_NOACK,
CMD_RD_NOACK,
};
static char const *cmd_string[] = {
[CMD_WR] = "WR",
[CMD_RD] = "RD",
[CMD_WR_NOACK] = "WR NOACK",
[CMD_RD_NOACK] = "RD NOACK",
};
enum bus_speeds {
SPD_375K,
SPD_390K,
SPD_187K,
SPD_200K,
SPD_93K,
SPD_97K,
SPD_46K,
SPD_50K
};
static const struct bsc_clk_param bsc_clk[] = {
[SPD_375K] = {
.hz = 375000,
.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
.div_mask = 0
},
[SPD_390K] = {
.hz = 390000,
.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
.div_mask = 0
},
[SPD_187K] = {
.hz = 187500,
.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
.div_mask = 0
},
[SPD_200K] = {
.hz = 200000,
.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
.div_mask = 0
},
[SPD_93K] = {
.hz = 93750,
.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
.div_mask = BSC_CTL_REG_DIV_CLK_MASK
},
[SPD_97K] = {
.hz = 97500,
.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
.div_mask = BSC_CTL_REG_DIV_CLK_MASK
},
[SPD_46K] = {
.hz = 46875,
.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
.div_mask = BSC_CTL_REG_DIV_CLK_MASK
},
[SPD_50K] = {
.hz = 50000,
.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
.div_mask = BSC_CTL_REG_DIV_CLK_MASK
}
};
struct brcmstb_i2c_dev {
struct device *device;
void __iomem *base;
void __iomem *irq_base;
int irq;
struct bsc_regs *bsc_regmap;
struct i2c_adapter adapter;
struct completion done;
bool is_suspended;
u32 clk_freq_hz;
int data_regsz;
};
/* register accessors for both be and le cpu arch */
#ifdef CONFIG_CPU_BIG_ENDIAN
#define __bsc_readl(_reg) ioread32be(_reg)
#define __bsc_writel(_val, _reg) iowrite32be(_val, _reg)
#else
#define __bsc_readl(_reg) ioread32(_reg)
#define __bsc_writel(_val, _reg) iowrite32(_val, _reg)
#endif
#define bsc_readl(_dev, _reg) \
__bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg))
#define bsc_writel(_dev, _val, _reg) \
__bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev)
{
return (N_DATA_REGS * dev->data_regsz);
}
static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev)
{
return dev->data_regsz;
}
static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev,
bool int_en)
{
if (int_en)
/* Enable BSC CTL interrupt line */
dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;
else
/* Disable BSC CTL interrupt line */
dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;
barrier();
bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
}
static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)
{
struct brcmstb_i2c_dev *dev = devid;
u32 status_bsc_ctl = bsc_readl(dev, ctl_reg);
u32 status_iic_intrp = bsc_readl(dev, iic_enable);
dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n",
status_bsc_ctl, status_iic_intrp);
if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))
return IRQ_NONE;
brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
complete_all(&dev->done);
dev_dbg(dev->device, "isr handled");
return IRQ_HANDLED;
}
/* Wait for device to be ready */
static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)
{
unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {
if (time_after(jiffies, timeout))
return -ETIMEDOUT;
cpu_relax();
}
return 0;
}
/* i2c xfer completion function, handles both irq and polling mode */
static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev)
{
int ret = 0;
unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);
if (dev->irq >= 0) {
if (!wait_for_completion_timeout(&dev->done, timeout))
ret = -ETIMEDOUT;
} else {
/* we are in
|