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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright Intel Corporation (C) 2017.
*
* Based on the i2c-axxia.c driver.
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/iopoll.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#define ALTR_I2C_TFR_CMD 0x00 /* Transfer Command register */
#define ALTR_I2C_TFR_CMD_STA BIT(9) /* send START before byte */
#define ALTR_I2C_TFR_CMD_STO BIT(8) /* send STOP after byte */
#define ALTR_I2C_TFR_CMD_RW_D BIT(0) /* Direction of transfer */
#define ALTR_I2C_RX_DATA 0x04 /* RX data FIFO register */
#define ALTR_I2C_CTRL 0x08 /* Control register */
#define ALTR_I2C_CTRL_RXT_SHFT 4 /* RX FIFO Threshold */
#define ALTR_I2C_CTRL_TCT_SHFT 2 /* TFER CMD FIFO Threshold */
#define ALTR_I2C_CTRL_BSPEED BIT(1) /* Bus Speed (1=Fast) */
#define ALTR_I2C_CTRL_EN BIT(0) /* Enable Core (1=Enable) */
#define ALTR_I2C_ISER 0x0C /* Interrupt Status Enable register */
#define ALTR_I2C_ISER_RXOF_EN BIT(4) /* Enable RX OVERFLOW IRQ */
#define ALTR_I2C_ISER_ARB_EN BIT(3) /* Enable ARB LOST IRQ */
#define ALTR_I2C_ISER_NACK_EN BIT(2) /* Enable NACK DET IRQ */
#define ALTR_I2C_ISER_RXRDY_EN BIT(1) /* Enable RX Ready IRQ */
#define ALTR_I2C_ISER_TXRDY_EN BIT(0) /* Enable TX Ready IRQ */
#define ALTR_I2C_ISR 0x10 /* Interrupt Status register */
#define ALTR_I2C_ISR_RXOF BIT(4) /* RX OVERFLOW IRQ */
#define ALTR_I2C_ISR_ARB BIT(3) /* ARB LOST IRQ */
#define ALTR_I2C_ISR_NACK BIT(2) /* NACK DET IRQ */
#define ALTR_I2C_ISR_RXRDY BIT(1) /* RX Ready IRQ */
#define ALTR_I2C_ISR_TXRDY BIT(0) /* TX Ready IRQ */
#define ALTR_I2C_STATUS 0x14 /* Status register */
#define ALTR_I2C_STAT_CORE BIT(0) /* Core Status (0=idle) */
#define ALTR_I2C_TC_FIFO_LVL 0x18 /* Transfer FIFO LVL register */
#define ALTR_I2C_RX_FIFO_LVL 0x1C /* Receive FIFO LVL register */
#define ALTR_I2C_SCL_LOW 0x20 /* SCL low count register */
#define ALTR_I2C_SCL_HIGH 0x24 /* SCL high count register */
#define ALTR_I2C_SDA_HOLD 0x28 /* SDA hold count register */
#define ALTR_I2C_ALL_IRQ (ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | \
ALTR_I2C_ISR_NACK | ALTR_I2C_ISR_RXRDY | \
ALTR_I2C_ISR_TXRDY)
#define ALTR_I2C_THRESHOLD 0 /* IRQ Threshold at 1 element */
#define ALTR_I2C_DFLT_FIFO_SZ 4
#define ALTR_I2C_TIMEOUT 100000 /* 100ms */
#define ALTR_I2C_XFER_TIMEOUT (msecs_to_jiffies(250))
/**
* altr_i2c_dev - I2C device context
* @base: pointer to register struct
* @msg: pointer to current message
* @msg_len: number of bytes transferred in msg
* @msg_err: error code for completed message
* @msg_complete: xfer completion object
* @dev: device reference
* @adapter: core i2c abstraction
* @i2c_clk: clock reference for i2c input clock
* @bus_clk_rate: current i2c bus clock rate
* @buf: ptr to msg buffer for easier use.
* @fifo_size: size of the FIFO passed in.
* @isr_mask: cached copy of local ISR enables.
* @isr_status: cached copy of local ISR status.
* @lock: spinlock for IRQ synchronization.
*/
struct altr_i2c_dev {
void __iomem *base;
struct i2c_msg *msg;
size_t msg_len;
int msg_err;
struct completion msg_complete;
struct device *dev;
struct i2c_adapter adapter;
struct clk *i2c_clk;
u32 bus_clk_rate;
u8 *buf;
u32 fifo_size;
u32 isr_mask;
u32 isr_status;
spinlock_t lock; /* IRQ synchronization */
};
static void
altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable)
{
unsigned long flags;
u32 int_en;
spin_lock_irqsave(&idev->lock, flags);
int_en = readl(idev->base + ALTR_I2C_ISER);
if (enable)
idev->isr_mask = int_en | mask;
else
idev->isr_mask = int_en & ~mask;
writel(idev->isr_mask, idev->base + ALTR_I2C_ISER);
spin_unlock_irqrestore(&idev->lock, flags);
}
static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask)
{
u32 int_en = readl(idev->base + ALTR_I2C_ISR);
writel(int_en | mask, idev->base + ALTR_I2C_ISR);
}
static void altr_i2c_core_disable(struct altr_i2c_dev *idev)
{
u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
}
static void altr_i2c_core_enable(struct altr_i2c_dev *idev)
{
u32 tmp = readl(idev->base + ALTR_I2C_CTRL);
writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL);
}
static void altr_i2c_reset(struct altr_i2c_dev *idev)
{
altr_i2c_core_disable(idev);
altr_i2c_core_enable(idev);
}
static inline void altr_i2c_stop(struct altr_i2c_dev *idev)
{
writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD);
}
static void altr_i2c_init(struct altr_i2c_dev *idev)
{
u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
u32 tmp = (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_RXT_SHFT) |
(ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_TCT_SHFT);
u32 t_high, t_low;
if (idev->bus_clk_rate <= 100000) {
tmp &= ~ALTR_I2C_CTRL_BSPEED;
/* Standard mode SCL 50/50 */
t_high = divisor * 1 / 2;
t_low = divisor * 1 / 2;
} else {
tmp |= ALTR_I2C_CTRL_BSPEED;
/* Fast mode SCL 33/66 */
t_high = divisor * 1 / 3;
t_low = divisor * 2 / 3;
}
writel(tmp, idev->base + ALTR_I2C_CTRL);
dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
idev->bus_clk_rate, clk_mhz, divisor);
/* Reset controller */
altr_i2c_reset(idev);
/* SCL High Time */
writel(t_high, idev->base + ALTR_I2C_SCL_HIGH);
/* SCL Low Time */
writel(t_low, idev->base + ALTR_I2C_SCL_LOW);
/* SDA Hold Time, 300ns */
writel(div_u64(300 * clk_mhz, 1000), idev->base + ALTR_I2C_SDA_HOLD);
/* Mask all master interrupt bits */
altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false);
}
/**
* altr_i2c_transfer - On the last byte to be transmitted, send
* a Stop bit on the last byte.
*/
static void altr_i2c_transfer(struct altr_i2c_dev *idev, u32 data)
{
/* On the last byte to be transmitted, send STOP */
if (idev->msg_len == 1)
data |= ALTR_I2C_TFR_CMD_STO;
if (idev->msg_len > 0)
writel(data, idev->base + ALTR_I2C_TFR_CMD);
}
/**
* altr_i2c_empty_rx_fifo - Fetch data from RX FIFO until end of
* transfer. Send a Stop bit on the last byte.
*/
static void altr_i2c_empty_rx_fifo(struct altr_i2c_dev *idev)
{
size_t rx_fifo_avail = readl(idev->base + ALTR_I2C_RX_FIFO_LVL);
int bytes_to_transfer = min(rx_fifo_avail, idev->msg_len);
while (bytes_to_transfer-- > 0) {
*idev->buf++ = readl(idev->base + ALTR_I2C_RX_DATA);
idev->msg_len--;
altr_i2c_transfer(idev, 0);
}
}
/**
* altr_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
* @return: Number of bytes left to transfer.
*/
static int altr_i2c_fill_tx_fifo(struct altr_i2c_dev *idev)
{
size_t tx_fifo_avail = idev->fifo_size - readl(idev->base +
ALTR_I2C_TC_FIFO_LVL);
int bytes_to_transfer = min(tx_fifo_avail, idev->msg_len);
int ret = idev->msg_len - bytes_to_transfer;
while (bytes_to_transfer-- > 0) {
altr_i2c_transfer(idev, *idev->buf++);
idev->msg_len--;
}
return ret;
}
static irqreturn_t altr_i2c_isr_quick(int irq, void *_dev)
{
struct altr_i2c_dev *idev = _dev;
irqreturn_t ret = IRQ_HANDLED;
/* Read IRQ status but only interested in Enabled IRQs. */
idev->isr_status = readl(idev->base + ALTR_I2C_ISR) & idev->isr_mask;
if (idev->isr_status)
ret = IRQ_WAKE_THREAD;
return ret;
}
static irqreturn_t altr_i2c_isr(int irq, void *_dev)
{
int ret;
bool read, finish = false;
struct altr_i2c_dev *idev = _dev;
u32 status = idev->isr_status;
if (!idev->msg) {
dev_warn(idev->dev, "unexpected interrupt\n");
altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ);
return IRQ_HANDLED;
}
read = (idev->msg->flags & I2C_M_RD) != 0;
/* handle Lost Arbitration */
if (unlikely(status & ALTR_I2C_ISR_ARB)) {
altr_i2c_int_clear(idev, ALTR_I2C_ISR_ARB);
idev->msg_err = -EAGAIN;
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