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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
*
* Copyright (C) 2020 Nvidia Technologies Ltd.
*/
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include "pmbus.h"
/* Vendor specific registers. */
#define MP2975_MFR_APS_HYS_R2 0x0d
#define MP2975_MFR_SLOPE_TRIM3 0x1d
#define MP2975_MFR_VR_MULTI_CONFIG_R1 0x0d
#define MP2975_MFR_VR_MULTI_CONFIG_R2 0x1d
#define MP2975_MFR_APS_DECAY_ADV 0x56
#define MP2975_MFR_DC_LOOP_CTRL 0x59
#define MP2975_MFR_OCP_UCP_PHASE_SET 0x65
#define MP2975_MFR_VR_CONFIG1 0x68
#define MP2975_MFR_READ_CS1_2 0x82
#define MP2975_MFR_READ_CS3_4 0x83
#define MP2975_MFR_READ_CS5_6 0x84
#define MP2975_MFR_READ_CS7_8 0x85
#define MP2975_MFR_READ_CS9_10 0x86
#define MP2975_MFR_READ_CS11_12 0x87
#define MP2975_MFR_READ_IOUT_PK 0x90
#define MP2975_MFR_READ_POUT_PK 0x91
#define MP2975_MFR_READ_VREF_R1 0xa1
#define MP2975_MFR_READ_VREF_R2 0xa3
#define MP2975_MFR_OVP_TH_SET 0xe5
#define MP2975_MFR_UVP_SET 0xe6
#define MP2975_VOUT_FORMAT BIT(15)
#define MP2975_VID_STEP_SEL_R1 BIT(4)
#define MP2975_IMVP9_EN_R1 BIT(13)
#define MP2975_VID_STEP_SEL_R2 BIT(3)
#define MP2975_IMVP9_EN_R2 BIT(12)
#define MP2975_PRT_THRES_DIV_OV_EN BIT(14)
#define MP2975_DRMOS_KCS GENMASK(13, 12)
#define MP2975_PROT_DEV_OV_OFF 10
#define MP2975_PROT_DEV_OV_ON 5
#define MP2975_SENSE_AMPL BIT(11)
#define MP2975_SENSE_AMPL_UNIT 1
#define MP2975_SENSE_AMPL_HALF 2
#define MP2975_VIN_UV_LIMIT_UNIT 8
#define MP2975_MAX_PHASE_RAIL1 8
#define MP2975_MAX_PHASE_RAIL2 4
#define MP2975_PAGE_NUM 2
#define MP2975_RAIL2_FUNC (PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | \
PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT | \
PMBUS_PHASE_VIRTUAL)
struct mp2975_data {
struct pmbus_driver_info info;
int vout_scale;
int vid_step[MP2975_PAGE_NUM];
int vref[MP2975_PAGE_NUM];
int vref_off[MP2975_PAGE_NUM];
int vout_max[MP2975_PAGE_NUM];
int vout_ov_fixed[MP2975_PAGE_NUM];
int vout_format[MP2975_PAGE_NUM];
int curr_sense_gain[MP2975_PAGE_NUM];
};
#define to_mp2975_data(x) container_of(x, struct mp2975_data, info)
static int mp2975_read_byte_data(struct i2c_client *client, int page, int reg)
{
switch (reg) {
case PMBUS_VOUT_MODE:
/*
* Enforce VOUT direct format, since device allows to set the
* different formats for the different rails. Conversion from
* VID to direct provided by driver internally, in case it is
* necessary.
*/
return PB_VOUT_MODE_DIRECT;
default:
return -ENODATA;
}
}
static int
mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg,
u16 mask)
{
int ret = pmbus_read_word_data(client, page, phase, reg);
return (ret > 0) ? ret & mask : ret;
}
static int
mp2975_vid2direct(int vrf, int val)
{
switch (vrf) {
case vr12:
if (val >= 0x01)
return 250 + (val - 1) * 5;
break;
case vr13:
if (val >= 0x01)
return 500 + (val - 1) * 10;
break;
case imvp9:
if (val >= 0x01)
return 200 + (val - 1) * 10;
break;
default:
return -EINVAL;
}
return 0;
}
static int
mp2975_read_phase(struct i2c_client *client, struct mp2975_data *data,
int page, int phase, u8 reg)
{
int ph_curr, ret;
ret = pmbus_read_word_data(client, page, phase, reg);
if (ret < 0)
return ret;
if (!((phase + 1) % MP2975_PAGE_NUM))
ret >>= 8;
ret &= 0xff;
/*
* Output value is calculated as: (READ_CSx / 80 – 1.23) / (Kcs * Rcs)
* where:
* - Kcs is the DrMOS current sense gain of power stage, which is
* obtained from the register MP2975_MFR_VR_CONFIG1, bits 13-12 with
* the following selection of DrMOS (data->curr_sense_gain[page]):
* 00b - 5µA/A, 01b - 8.5µA/A, 10b - 9.7µA/A, 11b - 10µA/A.
* - Rcs is the internal phase current sense resistor which is constant
* value 1kΩ.
*/
ph_curr = ret * 100 - 9800;
/*
* Current phase sensing, providing by the device is not accurate
* for the light load. This because sampling of current occurrence of
* bit weight has a big deviation for light load. For handling such
* case phase current is represented as the maximum between the value
* calculated above and total rail current divided by number phases.
*/
ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT);
if (ret < 0)
return ret;
return max_t(int, DIV_ROUND_CLOSEST(ret, data->info.phases[page]),
DIV_ROUND_CLOSEST(ph_curr, data->curr_sense_gain[page]));
}
static int
mp2975_read_phases(struct i2c_client *client, struct mp2975_data *data,
int page, int phase)
{
int ret;
if (page) {
switch (phase) {
case 0 ... 1:
ret = mp2975_read_phase(client, data, page, phase,
MP2975_MFR_READ_CS7_8);
break;
case 2 ... 3:
ret = mp2975_read_phase(client, data, page, phase,
MP2975_MFR_READ_CS9_10);
break;
case 4 ... 5:
ret = mp2975_read_phase(client, data, page, phase,
MP2975_MFR_READ_CS11_12);
break;
default:
return -ENODATA;
}
} else {
switch (phase) {
case 0 ... 1:
ret = mp2975_read_phase(client, data, page, phase,
MP2975_MFR_READ_CS1_2);
break;
case 2 ... 3:
ret = mp2975_read_phase(client, data, page, phase,
MP2975_MFR_READ_CS3_4);
break;
case 4 ... 5:
ret = mp2975_read_phase(client, data, page, phase,
MP2975_MFR_READ_CS5_6);
break;
case 6 ... 7:
ret = mp2975_read_phase(client, data, page, phase,
MP2975_MFR_READ_CS7_8);
break;
case 8 ... 9:
ret = mp2975_read_phase(client, data, page, phase,
MP2975_MFR_READ_CS9_10);
break;
case 10 ... 11:
ret = mp2975_read_phase(client, data, page, phase,
MP2975_MFR_READ_CS11_12);
break;
default:
return -ENODATA;
}
}
return ret;
}
static int mp2975_read_word_data(struct i2c_client *client, int page,
int phase, int reg)
{
const struct pmbus_driver_info *info = pmbus_get_driver_info(client);
|