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/*
* Copyright (c) 2016 Google, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or later as
* published by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/gpio/consumer.h>
#include <linux/delay.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/sysfs.h>
#include <linux/regmap.h>
/* ASPEED PWM & FAN Tach Register Definition */
#define ASPEED_PTCR_CTRL 0x00
#define ASPEED_PTCR_CLK_CTRL 0x04
#define ASPEED_PTCR_DUTY0_CTRL 0x08
#define ASPEED_PTCR_DUTY1_CTRL 0x0c
#define ASPEED_PTCR_TYPEM_CTRL 0x10
#define ASPEED_PTCR_TYPEM_CTRL1 0x14
#define ASPEED_PTCR_TYPEN_CTRL 0x18
#define ASPEED_PTCR_TYPEN_CTRL1 0x1c
#define ASPEED_PTCR_TACH_SOURCE 0x20
#define ASPEED_PTCR_TRIGGER 0x28
#define ASPEED_PTCR_RESULT 0x2c
#define ASPEED_PTCR_INTR_CTRL 0x30
#define ASPEED_PTCR_INTR_STS 0x34
#define ASPEED_PTCR_TYPEM_LIMIT 0x38
#define ASPEED_PTCR_TYPEN_LIMIT 0x3C
#define ASPEED_PTCR_CTRL_EXT 0x40
#define ASPEED_PTCR_CLK_CTRL_EXT 0x44
#define ASPEED_PTCR_DUTY2_CTRL 0x48
#define ASPEED_PTCR_DUTY3_CTRL 0x4c
#define ASPEED_PTCR_TYPEO_CTRL 0x50
#define ASPEED_PTCR_TYPEO_CTRL1 0x54
#define ASPEED_PTCR_TACH_SOURCE_EXT 0x60
#define ASPEED_PTCR_TYPEO_LIMIT 0x78
/* ASPEED_PTCR_CTRL : 0x00 - General Control Register */
#define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART1 15
#define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_PART2 6
#define ASPEED_PTCR_CTRL_SET_PWMD_TYPE_MASK (BIT(7) | BIT(15))
#define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1 14
#define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2 5
#define ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK (BIT(6) | BIT(14))
#define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1 13
#define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2 4
#define ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK (BIT(5) | BIT(13))
#define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1 12
#define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2 3
#define ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK (BIT(4) | BIT(12))
#define ASPEED_PTCR_CTRL_FAN_NUM_EN(x) BIT(16 + (x))
#define ASPEED_PTCR_CTRL_PWMD_EN BIT(11)
#define ASPEED_PTCR_CTRL_PWMC_EN BIT(10)
#define ASPEED_PTCR_CTRL_PWMB_EN BIT(9)
#define ASPEED_PTCR_CTRL_PWMA_EN BIT(8)
#define ASPEED_PTCR_CTRL_CLK_SRC BIT(1)
#define ASPEED_PTCR_CTRL_CLK_EN BIT(0)
/* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */
/* TYPE N */
#define ASPEED_PTCR_CLK_CTRL_TYPEN_MASK GENMASK(31, 16)
#define ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT 24
#define ASPEED_PTCR_CLK_CTRL_TYPEN_H 20
#define ASPEED_PTCR_CLK_CTRL_TYPEN_L 16
/* TYPE M */
#define ASPEED_PTCR_CLK_CTRL_TYPEM_MASK GENMASK(15, 0)
#define ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT 8
#define ASPEED_PTCR_CLK_CTRL_TYPEM_H 4
#define ASPEED_PTCR_CLK_CTRL_TYPEM_L 0
/*
* ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control
* 0/1/2/3 register
*/
#define DUTY_CTRL_PWM2_FALL_POINT 24
#define DUTY_CTRL_PWM2_RISE_POINT 16
#define DUTY_CTRL_PWM2_RISE_FALL_MASK GENMASK(31, 16)
#define DUTY_CTRL_PWM1_FALL_POINT 8
#define DUTY_CTRL_PWM1_RISE_POINT 0
#define DUTY_CTRL_PWM1_RISE_FALL_MASK GENMASK(15, 0)
/* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */
#define TYPE_CTRL_FAN_MASK (GENMASK(5, 1) | GENMASK(31, 16))
#define TYPE_CTRL_FAN1_MASK GENMASK(31, 0)
#define TYPE_CTRL_FAN_PERIOD 16
#define TYPE_CTRL_FAN_MODE 4
#define TYPE_CTRL_FAN_DIVISION 1
#define TYPE_CTRL_FAN_TYPE_EN 1
/* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */
/* bit [0,1] at 0x20, bit [2] at 0x60 */
#define TACH_PWM_SOURCE_BIT01(x) ((x) * 2)
#define TACH_PWM_SOURCE_BIT2(x) ((x) * 2)
#define TACH_PWM_SOURCE_MASK_BIT01(x) (0x3 << ((x) * 2))
#define TACH_PWM_SOURCE_MASK_BIT2(x) BIT((x) * 2)
/* ASPEED_PTCR_RESULT : 0x2c - Result Register */
#define RESULT_STATUS_MASK BIT(31)
#define RESULT_VALUE_MASK 0xfffff
/* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */
#define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART1 15
#define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_PART2 6
#define ASPEED_PTCR_CTRL_SET_PWMH_TYPE_MASK (BIT(7) | BIT(15))
#define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART1 14
#define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_PART2 5
#define ASPEED_PTCR_CTRL_SET_PWMG_TYPE_MASK (BIT(6) | BIT(14))
#define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART1 13
#define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_PART2 4
#define ASPEED_PTCR_CTRL_SET_PWMF_TYPE_MASK (BIT(5) | BIT(13))
#define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART1 12
#define ASPEED_PTCR_CTRL_SET_PWME_TYPE_PART2 3
#define ASPEED_PTCR_CTRL_SET_PWME_TYPE_MASK (BIT(4) | BIT(12))
#define ASPEED_PTCR_CTRL_PWMH_EN BIT(11)
#define ASPEED_PTCR_CTRL_PWMG_EN BIT(10)
#define ASPEED_PTCR_CTRL_PWMF_EN BIT(9)
#define ASPEED_PTCR_CTRL_PWME_EN BIT(8)
/* ASPEED_PTCR_CLK_EXT_CTRL : 0x44 - Clock Control Extension #1 Register */
/* TYPE O */
#define ASPEED_PTCR_CLK_CTRL_TYPEO_MASK GENMASK(15, 0)
#define ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT 8
#define ASPEED_PTCR_CLK_CTRL_TYPEO_H 4
#define ASPEED_PTCR_CLK_CTRL_TYPEO_L 0
#define PWM_MAX 255
#define M_PWM_DIV_H 0x00
#define M_PWM_DIV_L 0x05
#define M_PWM_PERIOD 0x5F
#define M_TACH_CLK_DIV 0x00
#define M_TACH_MODE 0x00
#define M_TACH_UNIT 0x1000
#define INIT_FAN_CTRL 0xFF
struct aspeed_pwm_tacho_data {
struct regmap *regmap;
unsigned long clk_freq;
bool pwm_present[8];
bool fan_tach_present[16];
u8 type_pwm_clock_unit[3];
u8 type_pwm_clock_division_h[3];
u8 type_pwm_clock_division_l[3];
u8 type_fan_tach_clock_division[3];
u16 type_fan_tach_unit[3];
u8 pwm_port_type[8];
u8 pwm_port_fan_ctrl[8];
u8 fan_tach_ch_source[16];
const struct attribute_group *groups[3];
};
enum type { TYPEM, TYPEN, TYPEO };
struct type_params {
u32 l_value;
u32 h_value;
u32 unit_value;
u32 clk_ctrl_mask;
u32 clk_ctrl_reg;
u32 ctrl_reg;
u32 ctrl_reg1;
};
static const struct type_params type_params[] = {
[TYPEM] = {
.l_value = ASPEED_PTCR_CLK_CTRL_TYPEM_L,
.h_value = ASPEED_PTCR_CLK_CTRL_TYPEM_H,
.unit_value = ASPEED_PTCR_CLK_CTRL_TYPEM_UNIT,
.clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEM_MASK,
.clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
.ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
.ctrl_reg1 = ASPEED_PTCR_TYPEM_CTRL1,
},
[TYPEN] = {
.l_value = ASPEED_PTCR_CLK_CTRL_TYPEN_L,
.h_value = ASPEED_PTCR_CLK_CTRL_TYPEN_H,
.unit_value = ASPEED_PTCR_CLK_CTRL_TYPEN_UNIT,
.clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEN_MASK,
.clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL,
.ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
.ctrl_reg1 = ASPEED_PTCR_TYPEN_CTRL1,
},
[TYPEO] = {
.l_value = ASPEED_PTCR_CLK_CTRL_TYPEO_L,
.h_value = ASPEED_PTCR_CLK_CTRL_TYPEO_H,
.unit_value = ASPEED_PTCR_CLK_CTRL_TYPEO_UNIT,
.clk_ctrl_mask = ASPEED_PTCR_CLK_CTRL_TYPEO_MASK,
.clk_ctrl_reg = ASPEED_PTCR_CLK_CTRL_EXT,
.ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
.ctrl_reg1 = ASPEED_PTCR_TYPEO_CTRL1,
}
};
enum pwm_port { PWMA, PWMB, PWMC, PWMD, PWME, PWMF, PWMG, PWMH };
struct pwm_port_params {
u32 pwm_en;
u32 ctrl_reg;
u32 type_part1;
u32 type_part2;
u32 type_mask;
u32 duty_ctrl_rise_point;
u32 duty_ctrl_fall_point;
u32 duty_ctrl_reg;
u32 duty_ctrl_rise_fall_mask;
};
static const struct pwm_port_params pwm_port_params[] = {
[PWMA] = {
.pwm_en = ASPEED_PTCR_CTRL_PWMA_EN,
.ctrl_reg = ASPEED_PTCR_CTRL,
.type_part1 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART1,
.type_part2 = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_PART2,
.type_mask = ASPEED_PTCR_CTRL_SET_PWMA_TYPE_MASK,
.duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
.duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
.duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
.duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM1_RISE_FALL_MASK,
},
[PWMB] = {
.pwm_en = ASPEED_PTCR_CTRL_PWMB_EN,
.ctrl_reg = ASPEED_PTCR_CTRL,
.type_part1 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART1,
.type_part2 = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_PART2,
.type_mask = ASPEED_PTCR_CTRL_SET_PWMB_TYPE_MASK,
.duty_ctrl_rise_point = DUTY_CTRL_PWM2_RISE_POINT,
.duty_ctrl_fall_point = DUTY_CTRL_PWM2_FALL_POINT,
.duty_ctrl_reg = ASPEED_PTCR_DUTY0_CTRL,
.duty_ctrl_rise_fall_mask = DUTY_CTRL_PWM2_RISE_FALL_MASK,
},
[PWMC] = {
.pwm_en = ASPEED_PTCR_CTRL_PWMC_EN,
.ctrl_reg = ASPEED_PTCR_CTRL,
.type_part1 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART1,
.type_part2 = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_PART2,
.type_mask = ASPEED_PTCR_CTRL_SET_PWMC_TYPE_MASK,
.duty_ctrl_rise_point = DUTY_CTRL_PWM1_RISE_POINT,
.duty_ctrl_fall_point = DUTY_CTRL_PWM1_FALL_POINT,
.duty_ctrl_reg
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