/*
* Copyright 1993-2003 NVIDIA, Corporation
* Copyright 2006 Dave Airlie
* Copyright 2007 Maarten Maathuis
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "drmP.h"
#include "drm_crtc_helper.h"
#include "nouveau_drv.h"
#include "nouveau_encoder.h"
#include "nouveau_connector.h"
#include "nouveau_crtc.h"
#include "nouveau_fb.h"
#include "nouveau_hw.h"
#include "nvreg.h"
#include "nouveau_fbcon.h"
static int
nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
struct drm_framebuffer *old_fb);
static void
crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
{
NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
crtcstate->CRTC[index]);
}
static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
{
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
}
crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
}
static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
{
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
nv_crtc->sharpness = level;
if (level < 0) /* blur is in hw range 0x3f -> 0x20 */
level += 0x40;
regp->ramdac_634 = level;
NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
}
#define PLLSEL_VPLL1_MASK \
(NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
| NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
#define PLLSEL_VPLL2_MASK \
(NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
| NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
#define PLLSEL_TV_MASK \
(NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
| NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
| NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
| NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
/* NV4x 0x40.. pll notes:
* gpu pll: 0x4000 + 0x4004
* ?gpu? pll: 0x4008 + 0x400c
* vpll1: 0x4010 + 0x4014
* vpll2: 0x4018 + 0x401c
* mpll: 0x4020 + 0x4024
* mpll: 0x4038 + 0x403c
*
* the first register of each pair has some unknown details:
* bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
* bits 20-23: (mpll) something to do with post divider?
* bits 28-31: related to single stage mode? (bit 8/12)
*/
static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
{
struct drm_device *dev = crtc->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct nv04_mode_state *state = &dev_priv->mode_reg;
struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
struct nouveau_pll_vals *pv = ®p->pllvals;
struct pll_lims pll_lim;
if (get_pll_limits(dev, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, &pll_lim))
return;
/* NM2 == 0 is used to determine single stage mode on two stage plls */
pv->NM2 = 0;
/* for newer nv4x the blob uses only the first stage of the vpll below a
* certain clock. for a certain nv4b this is 150MHz. since the max
* output frequency of the first stage for this card is 300MHz, it is
* assumed the threshold is given by vco1 maxfreq/2
*/
/* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
* not 8, others unknown), the blob always uses both plls. no problem
* has yet been observed in allowing the use a single stage pll on all
* nv43 however. the behaviour of single stage use is untested on nv40
*/
if (dev_priv->chipset > 0x40 && dot_clock <= (pll_lim.vco1.maxfreq /