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// SPDX-License-Identifier: GPL-2.0
//
// Ingenic JZ47xx KMS driver
//
// Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_drv.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_irq.h>
#include <drm/drm_managed.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <drm/drm_plane.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_simple_kms_helper.h>
#include <drm/drm_vblank.h>
#define JZ_REG_LCD_CFG 0x00
#define JZ_REG_LCD_VSYNC 0x04
#define JZ_REG_LCD_HSYNC 0x08
#define JZ_REG_LCD_VAT 0x0C
#define JZ_REG_LCD_DAH 0x10
#define JZ_REG_LCD_DAV 0x14
#define JZ_REG_LCD_PS 0x18
#define JZ_REG_LCD_CLS 0x1C
#define JZ_REG_LCD_SPL 0x20
#define JZ_REG_LCD_REV 0x24
#define JZ_REG_LCD_CTRL 0x30
#define JZ_REG_LCD_STATE 0x34
#define JZ_REG_LCD_IID 0x38
#define JZ_REG_LCD_DA0 0x40
#define JZ_REG_LCD_SA0 0x44
#define JZ_REG_LCD_FID0 0x48
#define JZ_REG_LCD_CMD0 0x4C
#define JZ_REG_LCD_DA1 0x50
#define JZ_REG_LCD_SA1 0x54
#define JZ_REG_LCD_FID1 0x58
#define JZ_REG_LCD_CMD1 0x5C
#define JZ_LCD_CFG_SLCD BIT(31)
#define JZ_LCD_CFG_PS_DISABLE BIT(23)
#define JZ_LCD_CFG_CLS_DISABLE BIT(22)
#define JZ_LCD_CFG_SPL_DISABLE BIT(21)
#define JZ_LCD_CFG_REV_DISABLE BIT(20)
#define JZ_LCD_CFG_HSYNCM BIT(19)
#define JZ_LCD_CFG_PCLKM BIT(18)
#define JZ_LCD_CFG_INV BIT(17)
#define JZ_LCD_CFG_SYNC_DIR BIT(16)
#define JZ_LCD_CFG_PS_POLARITY BIT(15)
#define JZ_LCD_CFG_CLS_POLARITY BIT(14)
#define JZ_LCD_CFG_SPL_POLARITY BIT(13)
#define JZ_LCD_CFG_REV_POLARITY BIT(12)
#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)
#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)
#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)
#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)
#define JZ_LCD_CFG_18_BIT BIT(7)
#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4))
#define JZ_LCD_CFG_MODE_GENERIC_16BIT 0
#define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7)
#define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6)
#define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1
#define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2
#define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 3
#define JZ_LCD_CFG_MODE_TV_OUT_P 4
#define JZ_LCD_CFG_MODE_TV_OUT_I 6
#define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 8
#define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN 9
#define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 10
#define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN 11
#define JZ_LCD_CFG_MODE_8BIT_SERIAL 12
#define JZ_LCD_CFG_MODE_LCM 13
#define JZ_LCD_VSYNC_VPS_OFFSET 16
#define JZ_LCD_VSYNC_VPE_OFFSET 0
#define JZ_LCD_HSYNC_HPS_OFFSET 16
#define JZ_LCD_HSYNC_HPE_OFFSET 0
#define JZ_LCD_VAT_HT_OFFSET 16
#define JZ_LCD_VAT_VT_OFFSET 0
#define JZ_LCD_DAH_HDS_OFFSET 16
#define JZ_LCD_DAH_HDE_OFFSET 0
#define JZ_LCD_DAV_VDS_OFFSET 16
#define JZ_LCD_DAV_VDE_OFFSET 0
#define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
#define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
#define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
#define JZ_LCD_CTRL_RGB555 BIT(27)
#define JZ_LCD_CTRL_OFUP BIT(26)
#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
#define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
#define JZ_LCD_CTRL_EOF_IRQ BIT(13)
#define JZ_LCD_CTRL_SOF_IRQ BIT(12)
#define JZ_LCD_CTRL_OFU_IRQ BIT(11)
#define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
#define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
#define JZ_LCD_CTRL_DD_IRQ BIT(8)
#define JZ_LCD_CTRL_QDD_IRQ BIT(7)
#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
#define JZ_LCD_CTRL_LSB_FISRT BIT(5)
#define JZ_LCD_CTRL_DISABLE BIT(4)
#define JZ_LCD_CTRL_ENABLE BIT(3)
#define JZ_LCD_CTRL_BPP_1 0x0
#define JZ_LCD_CTRL_BPP_2 0x1
#define JZ_LCD_CTRL_BPP_4 0x2
#define JZ_LCD_CTRL_BPP_8 0x3
#define JZ_LCD_CTRL_BPP_15_16 0x4
#define JZ_LCD_CTRL_BPP_18_24 0x5
#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | (0x7 << 0))
#define JZ_LCD_CMD_SOF_IRQ BIT(31)
#define JZ_LCD_CMD_EOF_IRQ BIT(30)
#define JZ_LCD_CMD_ENABLE_PAL BIT(28)
#define JZ_LCD_SYNC_MASK 0x3ff
#define JZ_LCD_STATE_EOF_IRQ BIT(5)
#define JZ_LCD_STATE_SOF_IRQ BIT(4)
#define JZ_LCD_STATE_DISABLED BIT(0)
struct ingenic_dma_hwdesc {
u32 next;
u32 addr;
u32 id;
u32 cmd;
} __packed;
struct jz_soc_info {
bool needs_dev_clk;
unsigned int max_width, max_height;
};
struct ingenic_drm {
struct drm_device drm;
struct drm_plane primary;
struct drm_crtc crtc;
struct drm_encoder encoder;
struct device *dev;
struct regmap *map;
struct clk *lcd_clk, *pix_clk;
const struct jz_soc_info *soc_info;
struct ingenic_dma_hwdesc *dma_hwdesc;
dma_addr_t dma_hwdesc_phys;
bool panel_is_sharp;
};
static const u32 ingenic_drm_primary_formats[] = {
DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB8888,
};
static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case JZ_REG_LCD_IID:
case JZ_REG_LCD_SA0:
case JZ_REG_LCD_FID0:
case JZ_REG_LCD_CMD0:
case JZ_REG_LCD_SA1:
case JZ_REG_LCD_FID1:
case JZ_REG_LCD_CMD1:
return false;
default:
return true;
}
}
static const struct regmap_config ingenic_drm_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = JZ_REG_LCD_CMD1,
.writeable_reg = ingenic_drm_writeable_reg,
};
static inline struct ingenic_drm *drm_device_get_priv(struct drm_device *drm)
{
return container_of(drm, struct ingenic_drm, drm);
}
static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc)
{
return container_of(crtc, struct ingenic_drm, crtc);
}
static inline struct ingenic_drm *
drm_encoder_get_priv(struct drm_encoder *encoder)
{
return container_of(encoder, struct ingenic_drm, encoder);
}
static inline struct ingenic_drm *drm_plane_get_priv(struct drm_plane *plane)
{
return container_of(plane, struct ingenic_drm, primary);
}
static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
regmap_write(priv->map, JZ_REG_LCD_STATE, 0);
regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
JZ_LCD_CTRL_ENABLE | JZ_LCD_CTRL_DISABLE,
JZ_LCD_CTRL_ENABLE);
drm_crtc_vblank_on(crtc);
}
static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{
struct ingenic_drm *priv = drm_crtc_get_priv(crtc);
unsigned int var;
drm_crtc_vblank_off(crtc);
regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
JZ_LCD_CTRL_DISABLE, JZ_LCD_CTRL_DISABLE);
regmap_read_poll_timeout(priv->map, JZ_REG_LCD_STATE, var,
var & JZ_LCD_STATE_DISABLED,
1000, 0);
}
static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv,
struct drm_display_mode *mode)
{
unsigned int vpe, vds, vde, vt, hpe, hds, hde, ht;
vpe = mode->vsync_end - mode->vsync_start;
vds = mode->vtotal - mode->vsync_start;
vde = vds + mode->vdisplay;
vt = vde + mode->vsync_start - mode->vdisplay;
|