1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Samsung Electronics Co., Ltd
*
* Authors:
* Andrzej Hajda <a.hajda@samsung.com>
* Maciej Purski <m.purski@samsung.com>
*/
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>
#include <drm/drmP.h>
#include <linux/gpio/consumer.h>
#include <linux/of_graph.h>
#include <linux/regulator/consumer.h>
#include <video/mipi_display.h>
#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
/* PPI layer registers */
#define PPI_STARTPPI 0x0104 /* START control bit */
#define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */
#define PPI_LANEENABLE 0x0134 /* Enables each lane */
#define PPI_TX_RX_TA 0x013C /* BTA timing parameters */
#define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
#define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
#define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */
#define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
#define PPI_START_FUNCTION 1
/* DSI layer registers */
#define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
#define DSI_LANEENABLE 0x0210 /* Enables each lane */
#define DSI_RX_START 1
/* Video path registers */
#define VP_CTRL 0x0450 /* Video Path Control */
#define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */
#define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */
#define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */
#define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */
#define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */
#define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */
#define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */
#define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */
#define VP_HTIM1 0x0454 /* Horizontal Timing Control 1 */
#define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16)
#define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0)
#define VP_HTIM2 0x0458 /* Horizontal Timing Control 2 */
#define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16)
#define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0)
#define VP_VTIM1 0x045C /* Vertical Timing Control 1 */
#define VP_VTIM1_VBP(v) FLD_VAL(v, 23, 16)
#define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0)
#define VP_VTIM2 0x0460 /* Vertical Timing Control 2 */
#define VP_VTIM2_VFP(v) FLD_VAL(v, 23, 16)
#define VP_VTIM2_VACT(v) FLD_VAL(v, 10, 0)
#define VP_VFUEN 0x0464 /* Video Frame Timing Update Enable */
/* LVDS registers */
#define LV_MX0003 0x0480 /* Mux input bit 0 to 3 */
#define LV_MX0407 0x0484 /* Mux input bit 4 to 7 */
#define LV_MX0811 0x0488 /* Mux input bit 8 to 11 */
#define LV_MX1215 0x048C /* Mux input bit 12 to 15 */
#define LV_MX1619 0x0490 /* Mux input bit 16 to 19 */
#define LV_MX2023 0x0494 /* Mux input bit 20 to 23 */
#define LV_MX2427 0x0498 /* Mux input bit 24 to 27 */
#define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
/* Input bit numbers used in mux registers */
enum {
LVI_R0,
LVI_R1,
LVI_R2,
LVI_R3,
LVI_R4,
LVI_R5,
LVI_R6,
LVI_R7,
LVI_G0,
LVI_G1,
LVI_G2,
LVI_G3,
LVI_G4,
LVI_G5,
LVI_G6,
LVI_G7,
LVI_B0,
LVI_B1,
LVI_B2,
LVI_B3,
LVI_B4,
LVI_B5,
LVI_B6,
LVI_B7,
LVI_HS,
LVI_VS,
LVI_DE,
LVI_L0
};
#define LV_CFG 0x049C /* LVDS Configuration */
#define LV_PHY0 0x04A0 /* LVDS PHY 0 */
#define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
#define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
#define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
#define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
/* System registers */
#define SYS_RST 0x0504 /* System Reset */
#define SYS_ID 0x0580 /* System ID */
#define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
#define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
#define SYS_RST_LCD BIT(2) /* Reset LCD controller */
#define SYS_RST_BM BIT(3) /* Reset Bus Management controller */
#define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
#define SYS_RST_REG BIT(5) /* Reset Register module */
#define LPX_PERIOD 2
#define TTA_SURE 3
#define TTA_GET 0x20000
/* Lane enable PPI and DSI register bits */
#define LANEENABLE_CLEN BIT(0)
#define LANEENABLE_L0EN BIT(1)
#define LANEENABLE_L1EN BIT(2)
#define LANEENABLE_L2EN BIT(3)
#define LANEENABLE_L3EN BIT(4)
/* LVCFG fields */
#define LV_CFG_LVEN BIT(0)
#define LV_CFG_LVDLINK BIT(1)
#define LV_CFG_CLKPOL1 BIT(2)
#define LV_CFG_CLKPOL2 BIT(3)
static const char * const tc358764_supplies[] = {
"vddc", "vddio", "vddlvds"
};
struct tc358764 {
struct device *dev;
struct drm_bridge bridge;
struct drm_connector connector;
struct regulator_bulk_data supplies[ARRAY_SIZE(tc358764_supplies)];
struct gpio_desc *gpio_reset;
struct drm_panel *panel;
int error;
};
static int tc358764_clear_error(struct tc358764 *ctx)
{
int ret = ctx->error;
ctx->error = 0;
return ret;
}
static void tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val)
{
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
ssize_t ret;
if (ctx->error)
return;
cpu_to_le16s(&addr);
ret = mipi_dsi_generic_read(dsi, &addr, sizeof(addr), val, sizeof(*val));
if (ret >= 0)
le32_to_cpus(val);
dev_dbg(ctx->dev, "read: %d, addr: %d\n", addr, *val);
}
static void tc358764_write(struct tc358764 *ctx, u16 addr, u32 val)
{
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
ssize_t ret;
u8 data[6];
if (ctx->error)
return;
data[0] = addr;
data[1] = addr >> 8;
data[2] = val;
data[3] = val >> 8;
data[4] = val >> 16;
data[5] = val >> 24;
ret = mipi_dsi_generic_write(dsi, data, sizeof(data));
if (ret < 0)
ctx->error = ret;
}
static inline struct tc358764 *bridge_to_tc358764(struct drm_bridge *bridge)
{
return container_of(bridge, struct tc358764, bridge);
}
static inline
struct tc358764 *connector_to_tc358764(struct drm_connector *connector)
{
return container_of(connector, struct tc358764, connector);
}
static int tc358764_init(struct tc358764 *ctx)
{
u32 v = 0;
tc358764_read(ctx, SYS_ID, &v);
if (ctx->error)
return tc358764_clear_error(ctx);
dev_info(ctx->dev, "ID: %#x\n", v);
/* configure PPI counters */
tc358764_write(ctx, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
tc358764_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD);
tc358764_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5);
tc358764_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5);
tc358764_write(ctx, PPI_D2S_CLRSIPOCOUNT, 5);
tc358764_write(ctx, PPI_D3S_CLRSIPOCOUNT, 5);
/* enable four data lanes and clock lane */
tc358764_write(ctx, PPI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN |
LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN);
tc358764_write(ctx, DSI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN |
LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN);
/* start */
tc358764_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION);
tc358764_write(ctx, DSI_STARTDSI, DSI_RX_START);
/* configure video path */
tc358764_write(ctx, VP_CTRL, VP_CTRL_VSDELAY(15) | VP_CTRL_RGB888(1) |
VP_CTRL_EVTMODE(1) | VP_CTRL_HSPOL | VP_CTRL_VSPOL);
/* reset PHY */
tc358764_write(ctx, LV_PHY0, LV_PHY0_RST(1) |
LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | LV_PHY0_ND(6));
tc358764_write(ctx, LV_PHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) |
LV_PHY0_ND(6));
/* reset bridge */
tc358764_write(ctx, SYS_RST, SYS_RST_LCD);
/* set bit order */
tc358764_write(ctx, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
tc358764_write(ctx, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
tc358764_write(ctx, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
tc358764_write(ctx, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
tc358764_write(ctx, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
tc358764_write(ctx, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
tc358764_write(ctx, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
tc358764_write(ctx, LV_CFG, LV_CFG_CLKPOL2 | LV_CFG_CLKPOL1 |
LV_CFG_LVEN);
return tc358764_clear_error(ctx);
}
static void tc358764_reset(struct tc358764 *ctx)
{
gpiod_set_value(ctx->gpio_reset, 1);
usleep_range(1000, 2000);
gpiod_set_value(ctx->gpio_reset, 0);
usleep_range(1000, 2000);
}
static int tc358764_get_modes(struct drm_connector *connector)
{
struct tc358764 *ctx =
|