/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "pp_debug.h"
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include "atom-types.h"
#include "atombios.h"
#include "processpptables.h"
#include "cgs_common.h"
#include "smumgr.h"
#include "hwmgr.h"
#include "hardwaremanager.h"
#include "rv_ppsmc.h"
#include "rv_hwmgr.h"
#include "power_state.h"
#include "rv_smumgr.h"
#include "pp_soc15.h"
#define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID 5
#define RAVEN_MINIMUM_ENGINE_CLOCK 800 //8Mhz, the low boundary of engine clock allowed on this chip
#define SCLK_MIN_DIV_INTV_SHIFT 12
#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 //100mhz
#define SMC_RAM_END 0x40000
static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic;
int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock_req);
struct phm_vq_budgeting_record rv_vqtable[] = {
/* _TBD
* CUs, SSP low, SSP High, Min Sclk Low, Min Sclk, High, AWD/non-AWD, DCLK, ECLK, Sustainable Sclk, Sustainable CUs */
{ 8, 0, 45, 0, 0, VQ_DisplayConfig_NoneAWD, 80000, 120000, 4, 0 },
};
static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps)
{
if (PhwRaven_Magic != hw_ps->magic)
return NULL;
return (struct rv_power_state *)hw_ps;
}
static const struct rv_power_state *cast_const_rv_ps(
const struct pp_hw_power_state *hw_ps)
{
if (PhwRaven_Magic != hw_ps->magic)
return NULL;
return (struct rv_power_state *)hw_ps;
}
static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr)
{
uint32_t table_size, i;
struct phm_vq_budgeting_table *ptable;
uint32_t num_entries = ARRAY_SIZE(rv_vqtable);
if (hwmgr->dyn_state.vq_budgeting_table != NULL)
return 0;
table_size = sizeof(struct phm_vq_budgeting_table) +
sizeof(struct phm_vq_budgeting_record) * (num_entries - 1);
ptable = kzalloc(table_size, GFP_KERNEL);
if (NULL == ptable)
return -ENOMEM;
ptable->numEntries = (uint8_t) num_entries;
for (i = 0; i < ptable->numEntries; i++) {
ptable->entries[i].ulCUs = rv_vqtable[i].ulCUs;
ptable->entries[i].ulSustainableSOCPowerLimitLow = rv_vqtable[i].ulSustainableSOCPowerLimitLow;
ptable->entries[i].ulSustainableSOCPowerLimitHigh = rv_vqtable[i].ulSustainableSOCPowerLimitHigh;
ptable->entries[i].ulMinSclkLow = rv_vqtable[i].ulMinSclkLow;
ptable->entries[i].ulMinSclkHigh = rv_vqtable[i].ulMinSclkHigh;
ptable->entries[i].ucDispConfig = rv_vqtable[i].ucDispConfig;
ptable->entries[i].ulDClk = rv_vqtable[i].ulDClk;
ptable->entries[i].ulEClk = rv_vqtable[i].ulEClk;
ptable->entries[i].ulSustainableSclk = rv_vqtable[i].ulSustainableSclk;
ptable->entries[i].ulSustainableCUs = rv_vqtable[i].ulSustainableCUs;
}
hwmgr->dyn_state.vq_budgeting_table = ptable;
return 0;
}
static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
{
struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend);
struct cgs_system_info sys_info = {0};
int result;
rv_hwmgr->ddi_power_gating_disabled = 0;