path: root/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm

/*
 * Copyright 2015-2017 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

/* To compile this assembly code:
 * PROJECT=vi ./sp3 cwsr_trap_handler_gfx8.asm -hex tmp.hex
 */

/**************************************************************************/
/*                      variables                                         */
/**************************************************************************/
var SQ_WAVE_STATUS_INST_ATC_SHIFT  = 23
var SQ_WAVE_STATUS_INST_ATC_MASK   = 0x00800000
var SQ_WAVE_STATUS_SPI_PRIO_SHIFT  = 1
var SQ_WAVE_STATUS_SPI_PRIO_MASK   = 0x00000006
var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT   = 0
var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE    = 1
var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT  = 3
var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE   = 29

var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT    = 12
var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE     = 9
var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT   = 8
var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE    = 6
var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT   = 24
var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE    = 3                     //FIXME  sq.blk still has 4 bits at this time while SQ programming guide has 3 bits

var SQ_WAVE_TRAPSTS_SAVECTX_MASK    =   0x400
var SQ_WAVE_TRAPSTS_EXCE_MASK       =   0x1FF                   // Exception mask
var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT   =   10
var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK   =   0x100
var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT  =   8
var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK    =   0x3FF
var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT   =   0x0
var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE    =   10
var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK   =   0xFFFFF800
var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT  =   11
var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE   =   21

var SQ_WAVE_IB_STS_RCNT_SHIFT           =   16                  //FIXME
var SQ_WAVE_IB_STS_RCNT_SIZE            =   4                   //FIXME
var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT   =   15                  //FIXME
var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE    =   1                   //FIXME
var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG   = 0x00007FFF    //FIXME

var SQ_BUF_RSRC_WORD1_ATC_SHIFT     =   24
var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT   =   27


/*      Save        */
var S_SAVE_BUF_RSRC_WORD1_STRIDE        =   0x00040000          //stride is 4 bytes
var S_SAVE_BUF_RSRC_WORD3_MISC          =   0x00807FAC          //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE

var S_SAVE_SPI_INIT_ATC_MASK            =   0x08000000          //bit[27]: ATC bit
var S_SAVE_SPI_INIT_ATC_SHIFT           =   27
var S_SAVE_SPI_INIT_MTYPE_MASK          =   0x70000000          //bit[30:28]: Mtype
var S_SAVE_SPI_INIT_MTYPE_SHIFT         =   28
var S_SAVE_SPI_INIT_FIRST_WAVE_MASK     =   0x04000000          //bit[26]: FirstWaveInTG
var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT    =   26

var S_SAVE_PC_HI_RCNT_SHIFT             =   28                  //FIXME  check with Brian to ensure all fields other than PC[47:0] can be used
var S_SAVE_PC_HI_RCNT_MASK              =   0xF0000000          //FIXME
var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT     =   27                  //FIXME
var S_SAVE_PC_HI_FIRST_REPLAY_MASK      =   0x08000000          //FIXME

var s_save_spi_init_lo              =   exec_lo
var s_save_spi_init_hi              =   exec_hi

                                                //tba_lo and tba_hi need to be saved/restored
var s_save_pc_lo            =   ttmp0           //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]}
var s_save_pc_hi            =   ttmp1
var s_save_exec_lo          =   ttmp2
var s_save_exec_hi          =   ttmp3
var s_save_status           =   ttmp4
var s_save_trapsts          =   ttmp5           //not really used until the end of the SAVE routine
var s_save_xnack_mask_lo    =   ttmp6
var s_save_xnack_mask_hi    =   ttmp7
var s_save_buf_rsrc0        =   ttmp8
var s_save_buf_rsrc1        =   ttmp9
var s_save_buf_rsrc2        =   ttmp10
var s_save_buf_rsrc3        =   ttmp11

var s_save_mem_offset       =   tma_lo
var s_save_alloc_size       =   s_save_trapsts